1 ACCEPTED SOLUTION
Accepted Solutions
Here some code extract to give you directions:
I used this link to get baseline: https://www.cnblogs.com/shangdawei/p/4753040.html
You will short MISO and MOSI outside. Here is STM32L4R5 in BGA132 @ 48MHz SYSCLK (low power) with 12 MHz SPI
IO_Pin_t SWDCLK_PIN = { // PB3 = SCK3
GPIOB, { GPIO_PIN_3, GPIO_MODE_AF_PP, GPIO_PULLDOWN, GPIO_SPEED_FREQ_VERY_HIGH, 6 }, // SPI3_AF
};
IO_Pin_t SWDO_PIN = { // PB5 = MOSI3 (bidir)
GPIOB, { GPIO_PIN_5, GPIO_MODE_AF_PP, GPIO_PULLDOWN, GPIO_SPEED_FREQ_HIGH, 6 }, // SPI3_AF
};
IO_Pin_t SWDI_PIN = { // PB4 = MISO3 (no use)
GPIOB, { GPIO_PIN_4, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_HIGH, 6 }, // SPI3_AF
};Next, some handy functions you will need:
uint8_t NibbleBitCounter[16] = {
0, // 0000
1, // 0001
1, // 0010
0, // 0011
1, // 0100
0, // 0101
0, // 0110
1, // 0111
//-------- symmetrical
1, // 1000
0, // 1001
0, // 1010
1, // 1011
0, // 1100
1, // 1101
1, // 1110
0 // 1111
};
//==== here we directly control SPI with FIFO, IP version 2
// you change the speed between read and write due to setup time difference.
// don't change the clock polarity dynamically, it's a side effect generator.
void SWD_SetSPICR1Normal(void);
void SWD_SetSPICR1Normal(void) {
SPI3->CR1 = ((SPI3->CR1)&0xFFC7)| (0<<3); // 24MHz
}
void SWD_SetSPICR1Slower(void);
void SWD_SetSPICR1Slower(void) {
SPI3->CR1 = ((SPI3->CR1)&0xFFC7)| (1<<3); // 12 MHz
}
void SWD_InitSPI(void) {
IO_PinConfigure(&SWDCLK_PIN); // PB3 = SCK3
IO_PinConfigure(&SWDO_PIN); // PB5 = MOSI3 (bidir)
IO_PinConfigure(&SWDI_PIN); // PB4 = MISO3 (no use)
__HAL_RCC_SPI3_CLK_ENABLE(); // Enable SPI2 clock
SPI3->CR1 = 0// (1<<15) // bidir = 1
// | (1<<14) // TX mode, output enabled
| (1<<9) // SSM=1
| (1<<8)
| (1<<7) // LSB first
| (0<<3) // prescaler div1 = 24 MHz
| (1<<2) // master mode
| (0<<1) // SCK is low when idle
| (1<<0); // the second clock edge is the data capture's
SPI3->CR2 = (0<<12) // RXNE when 8+bit in FIFO
| (7<<8); // 8 bit mode (n-1)
SPI3->CR1 |= (1<<6); // SPI enable
// now let's look at the generated signals...
}
void SWD_WaitIdle(void);
void SWD_WaitIdle(void) {
while(SPI3->SR & 1<<7); // wait while BUSY (transaction complete)
}
void SWD_Wait_u16(void);
void SWD_Wait_u16(void) {
while(SPI3->SR & (1<<12)); // while the FIFO can't digest 16 bit
}
void SWD_RxMode(void);
void SWD_RxMode(void) {
uint32_t moder = GPIOB->MODER;
moder = moder & ~(3<<10); // 0 = digital input
GPIOB->MODER = moder;
// SPI3->CR1 |= ~(1<<14); // TX mode
}
void SWD_TxMode(void);
void SWD_TxMode(void) {
uint32_t moder = GPIOB->MODER;
moder = moder | (2<<10); // 2 = output AF
GPIOB->MODER = moder;
// SPI3->CR1 &= ~(1<<14); // RX mode
}
void SWD_SetBits(uint8_t bits);
void SWD_SetBits(uint8_t bits) {
uint16_t r;
r = SPI3->CR2;
r &= ~(15<<8);
r |= (bits-1)<<8; // go to n-1 bit mode
SPI3->CR2 = r;
}
void FlushRxFifo(void);
void FlushRxFifo(void) {
SWD.flushed = *((__IO uint8_t *)&SPI3->DR);
SWD.flushed = *((__IO uint8_t *)&SPI3->DR);
SWD.flushed = *((__IO uint8_t *)&SPI3->DR);
SWD.flushed = *((__IO uint8_t *)&SPI3->DR);
}
void SWD_SwitchSPI(uint16_t sequence) {
SWD_WaitIdle();//SWD_Wait_u16();
// send the resynch
*(__IO uint16_t *)&SPI3->DR = 0xFFFF; // 16 bit
*(__IO uint16_t *)&SPI3->DR = 0xFFFF; // 32 bit
SWD_Wait_u16();//SWD_WaitIdle();
*(__IO uint16_t *)&SPI3->DR = 0xFFFF; // 48 bit
SWD_Wait_u16();//
*(__IO uint8_t *)&SPI3->DR = 0xFF; // 56 bit
SWD_Wait_u16();//SWD_WaitIdle();
*(__IO uint16_t *)&SPI3->DR = sequence;
SWD_WaitIdle();
FlushRxFifo();
}
void SWD_SyncSPI(void) {
SWD_WaitIdle();
// send the resynch
*(__IO uint16_t *)&SPI3->DR = 0xFFFF; // 16 bit
*(__IO uint16_t *)&SPI3->DR = 0xFFFF; // 32 bit
SWD_Wait_u16();//SWD_WaitIdle();
*(__IO uint16_t *)&SPI3->DR = 0xFFFF; // 48 bit
SWD_Wait_u16();//
*(__IO uint8_t *)&SPI3->DR = 0x3F; // 56 bit with 2 idle bits
SWD_WaitIdle();
FlushRxFifo();
}Some pictures
So to have a even fast communication, the SPI should have a special mode where the data register is split in MSB = bit length with R/W, LSB = data bits
Then the delay between packets could be minimized and average speed improved further. A true 3 wire interface would save 1 GPIO unless voltage shifting required outside.
