Showing results for 
Search instead for 
Did you mean: 

STM32 Major LPTIMER documentation shortcoming or is it a silicon design error???

Kent Swan

In looking at various LPTIM training documentation it's indicated very clearly that the LPTIMERs have a CNT reset as a function of setting bit 4 of the CR register.

As this is an important capability, there seems to be a number of reference documents documentation follow through problems.

For instance for the RM0410 Reference manual Rev 4 (STM32F76/F77) shows this bit in the register map on page 890/1418 but not in the register detailed description on page 1109/1954 .

In RM0393 Reference manual Rev 2 (STM32L4) the reset bit does not appear in either the detailed register description 886/1418 nor the register map on page 890/1418.

Can any one tell me if this is simply a failure in which sections of STM32 base documentation were copied into processor specific reference manuals or is the LPTIM reset actually missing or flawed on some of these processors. I'm hoping that it's simply a documentation oversight rather than a critical design error in the silicon.


> Where then do you report suspected or documented manual inaccuracies or need for clarification in a manner that it will eventually end up reviewed and, if appropriate, appear as a correction in a future revisions of those documents?

Here. I also brag about the documentation and lack of it frequently. It appears to have *some* effect, in the long run.


Kent Swan

Well Here it will be, I guess. Thanks for your tip.

As a FYI I'm writing a number of STM32 new how to's. One is how to run multiple I2S digital audio channels with Interrupts under DMA without tripping over your shoelaces. I run six 24 bit, 48 Khz audio channels on a STM32F413 with audio routing and filter processing without compromising other application code running under FreeRTOS. The second how-to is what I'm working on now which is a valid implementation of FreeRTOS Tickless mode on a STM32L462 using a 72Mhz system clock for operational performance and STOP1 with LPTIMx in order to get the lowest possible current draw when there's nothing to do. Basically sleep mode as demoed is pretty much useless as there is little to no power reduction.

Senior III

CNT register in LPTIM is read-only. If you need reset CNT register, use __HAL_LPTIM_RESET_COUNTER(&hlptim1);


if the refman is incorrecy, it should be fixed as it is the reference document. otherwise looking at different refman is not necessarily useful as the same ip may have evolved over time such as SPI, with programmable word length, 32bit fifos, and finally extra control bits...

The LPTIM documentation is notoriously sloppy. For example, one of its potentially most useful features is, that being asynchronous, you could potentially crank it at tens of MHz from an external signal, while the rest of the chip runs of low steam or sleeps.

Now show me the max clock spec of LPTIM in the DS.