STM32 ADC& DMA 4 channels

[Cesar cfg]

Posted on April 24, 2013 at 16:49

I am working with stm32F0 ADC & DMA peripherals and i have to convert 4 channels.The ADC  is triggered by the Timer1.

My problem is that i obtain  the result correct but there is a permutation between  2 channels(the second & the 4th).

So is any one have an idea to help me resolve the problem.

thanks #forum-says-no

[Cesar cfg]

Posted on April 29, 2013 at 11:42

I am still waiting for your answer !

[Tesla DeLorean]

Posted on April 29, 2013 at 16:28

I am still waiting for your answer !

On forums no answer means you've failed to attract interest to your post, or no one currently here has your specific issue, or has any useful comment. You might have to keep waiting. Your problem is compounded by the lack of a complete, free standing, example. I have better things to do than try to paste your code into a project, and add all the surrounding code. A clear description of the test case, the expected results, and observed results would also help. It's scanning backward, does that impact your expectations?

[Cesar cfg]

Posted on April 29, 2013 at 18:08

First i think that my post is clear and i have explained the problem well , second the scan direction  has no relation to my problem, third probably  there is a problem in the stm32F0 DMA and if you want you can try the example provided by ST to this core(ADC DMA example). 

Finally i didn't ask any one to wast his ''precious''  time  to ''

paste my code into a project'',i was  just looking for someone who has faced the same problem before.

and thank you Clive1 very match for your attention.  

[Tesla DeLorean]

Posted on April 29, 2013 at 23:10

Doing a quick validation on a STM32F0-Discovery, it looks to me like a TIM1 paced ADC of 4 Channels using DMA appears to generate consistent results for all 4 channels, across a large circular buffer.

One potential road block would be if the TIM pacing exceeds the conversion rate of the ADC.

[Cesar cfg]

Posted on April 30, 2013 at 09:18

I think that the TIM1 has no effect to our problem ,the same problem exist in the continuous mode.  

[raptorhal2]

Posted on April 30, 2013 at 15:01

esraf posted a similar, but not identical, problem on this forum 1/2/2013. Martin D replied that when the F0 ADC is calibrated, DMA advanced one position forward in the memory buffer. Go read esraf's post and see if that helps in understanding. And check the errata for your processor version to see if this is mentioned.

Cheers, Hal

[Cesar cfg]

Posted on April 30, 2013 at 15:22

can you give me the link of israf's post.

[Cesar cfg]

Posted on April 30, 2013 at 16:02

Thank you very match ,the problem was resolved.Just the calibration must be done before the DMA initialization to avoid the DMA memory increment.