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stack problem and privilege mode

ezrab
Associate II
Posted on June 16, 2011 at 14:48

hi.

i am using the STM32f103 chip and i am having all sord of problem that takes me to the Hard Fault inturpt .

when i check the SCB->CFSR register i am getting all sord of errors like :

''the processor has attempted to access a coprocessor.''

or

''The processor has attempted to execute an undefined instruction.''

i read alot and i found that i can change the privilege mode for safty reason so that the software cannot accsess importent register in the cpu i am hoping that it will help me solve the problems.

my question is how do i change that from what i can find i need to change the control register but how can i chnage that what is he called?

i found all that data here by the way:

http://www.st.com/stonline/products/literature/pm/15491.pdf

 

thanks.
23 REPLIES 23
Posted on June 22, 2011 at 18:37

Hex might be more helpful, pinning down where in your code the failure is occurring. the values of PC seem to be quite different, however LR seems to be quite uniform, what subroutine is being called at that point?

You'll need to look at the instructions being executed a PC during the failure, and look at the registers being used, and their values and the limits of the memory regions they are touching. You might need to dump out additional registers, as the fault is only pushing a subset.

Both int's and long's in the current context are 32-bit values.

static const char Hex[] = ''0123456789ABCDEF'';

void debug_longhex(unsigned long x)

{

  debug_char(Hex[((x >> 28) & 0x0F)]);

  debug_char(Hex[((x >> 24) & 0x0F)]);

  debug_char(Hex[((x >> 20) & 0x0F)]);

  debug_char(Hex[((x >> 16) & 0x0F)]);

  debug_char(Hex[((x >> 12) & 0x0F)]);

  debug_char(Hex[((x >>  8) & 0x0F)]);

  debug_char(Hex[((x >>  4) & 0x0F)]);

  debug_char(Hex[((x >>  0) & 0x0F)]);

  debug_char(0x0d);

}

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ezrab
Associate II
Posted on June 22, 2011 at 19:07

how do i know ''what subroutine is being called at that point?''

and how do i do that:

''You'll need to look at the instructions being executed a PC during the failure, and look at the registers being used, and their values and the limits of the memory regions they are touching. You might need to dump out additional registers, as the fault is only pushing a subset.''?

what does it means:''the fault is only pushing a subset.''

thanks.
Posted on June 22, 2011 at 20:20

Get a disassembly window, or listing of the code you are running. Correlate the address of the failure(s) with the addresses/instructions/registers in your compiled code.

The LR register points to the next instruction after the BL subroutine call, ie the return address.

The ARM architecture has 16 32-bit registers (technically it has more), the hard fault mechanism within the processor is pushing 7 of them on the stack, the remainder are still there. If the faulting instruction is using R4, you want to know the content of that register.

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Posted on June 22, 2011 at 20:40

1FFFF132             ChocolatePudding:

..

1FFFF136 69C9            ldr    r1, [r1, #28]   ; +$1C

..

1FFFF13E 4770            bx    lr

..

1FFFF2FA 2500            movs    r5, #0

1FFFF2FC F7FF FF19        bl    ChocolatePudding

1FFFF300 B9F0            cbnz    r0, loc_1FFFF340

PC = 1FFFF136 - The faulting instruction was touching the address R1+0x1C, what if R1=0x20010000

LR = 1FFFF301 - The return address suggests the code was in ChocolatePudding when it failed

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ezrab
Associate II
Posted on June 23, 2011 at 09:49

hi

here is the disassambly file and listing file.

what can i understand from that?

thanks.

Posted on June 23, 2011 at 15:53

what can i understand from that?

Without contemporaneous fault and register data, probably not much.

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ezrab
Associate II
Posted on June 24, 2011 at 09:00

hi.

after many test i found that it is probably caused by electromagnetic

http://www.google.com/search?hl=iw&safe=active&client=firefox-a&hs=OG1&rls=org.mozilla:he:official&sa=X&ei=czUETqOSNdGe-waRqpm7DQ&ved=0CB8QvgUoAA&q=inteference&nfpr=1

.

is there somthing i can do about it?

andi am using the STM32F103 now how do i know its resistence to EMI?

maybe there is abetter EMI STM32 chip.

how do know for each one the EMI resistence?

thanks.

Posted on June 24, 2011 at 18:12

Is this a problem with GPIO's or that the supply is being glitched repeatedly. If you have a hideously noisy supply, you might want to look at that first. If you can quantify the amount on noise you need to handle, you could use that number to qualify which parts might tolerate that.

Is there separation/isolation between the circuits pulling milli-amps and those pulling more industrial currents?

You need to examine the processor state, and the instructions being executed, at each faulting condition. You must decide if the fault is a result of external interference, or if you have a software error/bug which is causing the processor to touch memory it should not (ie stack out of bounds, indexing beyond an array, loading an uninitialized variable/pointer from the stack or other structures).

You will need to sit at the debugger and pin down a cause(s), I don't think this can be done remotely.

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ezrab
Associate II
Posted on June 26, 2011 at 07:41

hi.

this is probebly an outside interferance it is an Active Harmonic filter.

when i run the probram without the Enable it works fine but when i activate the Enable i get hard fault .

how do i know ''which parts might tolerate that''? how do i know the levels of tolerate for each device?

i attached the scamatic in Orcad .

thanks very much for your help.

Posted on June 27, 2011 at 20:12

A PDF might be helpful for those without access to OrCad.

You have a single 3.3V supply. What does that look like on that, how many millivolts of noise do you have in that supply? How much noise is in the 11V supply? How many layers does the PCB have?

Doesn't the design manual call for 4.7 uF of bulk capacitance on VDD3 of the STM32?

If you can't separate out the supplies, look at adding bulk and decoupling capacitor at components that have large and instantaneous current requirements.

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