SRAM3 Hard Fault when ECC is enabled

[JigarGoswami]

on STM32U575 when I enable the ECC, it is throwing a Hard Fault. I am just doing RAMCFG_Init() & StartECC() as of now. The system keeps resetting. TrustZone is enabled for the project, will that make any difference?

[ramprakash09]

Hi,

Firstly, it's important to understand that ECC is a method used to detect and correct errors in memory. When you enable ECC, the system will generate a Hard Fault when it detects an error that it cannot correct. This is a normal behavior of the system to prevent it from continuing with corrupted data.

However, if you are getting a Hard Fault immediately after enabling ECC, it could be due to an issue with the initialization of the ECC or the SRAM3.

Regards

[JigarGoswami]

Hi,

Thank you for the reply. As in this case, I have not enabled any interrupt for single or double errors. I am just enabling the ECC feature. So I believe there is some issue with the initialization.

I further checked the addresses of the Bus fault & MemManage fault and that is the same as the start address of the reserved last 64 KB of SRAM3 by ECC. So, again I believe that ECC trying to change this configuration is causing issues, but I don't know how to resolve that.

Correct me if I am wrong anywhere.

Thanks & regards

[Pavel A.]

Can you initialize (write) the whole RAM _before_ enabling ECC?

HardFault occurs if handling of other (un-masked) exceptions is not enabled so they propagate up to HardFault.

[FBL]

Hello @JigarGoswami, 

You may need to refer to the reference manual section 6.3.2 Error code correction (SRAM2, SRAM3, BKPSRAM).

When the ECC is enabled for SRAM3, only the first 256 Kbytes of SRAM3 are with ECC.
The next 192 Kbytes for STM32U575/585 or 512 Kbytes for STM32U59x/5Ax/5Fx/5Gx are without ECC, and the last block is used to store the ECC, so cannot be used for application.

[JigarGoswami]

Hello Belaid,

Thank you, I referred to that. 

I have one doubt. Will the last 64 KB of SRAM3 be reserved only when ECC is enabled for SRAM3?

or it does not matter if I enable ECC on SRAM3 or not.

What if I only enable ECC for SRAM2 alone? in that case, will it reserve the last 64 KB of SRAM3?

[FBL]

Hello again @JigarGoswami,

1. When ECC is deactivated (ECCE = 0), the SRAM3 ECC storage area can be read and written as other SRAM3 areas.
2. ECCE bit is automatically set after system reset in the related RAMCFG_MxCR. So, ECCE bit in RAMCFG_M2CR shouldn't affect RAMCFG_M3CR.

Hope this helps!

[PMera.1]

I was well beyond my wits end trying to understand what in the seven hells was raising a hard fault. Null pointer exception?! Where? SRAM3 Ecc...

Thanks a million.