SPI Transfer Less Than 8-bits

[steven239955_stm1]

Posted on November 15, 2011 at 22:57

I have been reading the SPI documentation for the STM32F4 and it is unclear to me how things function if you have a transfer that is less than 8-bits.

I have a piece of hardware that provides clock and data. There are 132 bits per transfer and new transfers occur approximately every 10us. I cannot change this. It is not clear to me from the documentation what happens after the last 4 clocks. Does the hardware wait 10us and complete the previous transfer with the first 4 bits of the following transfer? Can the receive buffer be read and the internal state reset so that the next transfer starts off looking for a full 8-bits?

[Tesla DeLorean]

Posted on November 16, 2011 at 00:14

A slave device is going to wait until the clocks start coming again, basically hanging. The STM32's are not particularly flexible with SPI bit lengths. You could let the clocks stop/start, and then cut the 132 bits you're interested in out of the stream.

I don't think there is a way to forestall the SPI transfer, but if you can count the clock pulses you might be able to ''reset'' the peripheral. You could create a circuit that generates some additional inter-message clocks, or one that doubles the SPI's clocking signal so 4-bits become 8-bits.