SPI Packing Mode

[tj]

Posted on March 26, 2017 at 17:43

Hi all,

i am using the STM32F030RC for a customer project. To SPI1 we have connected a SPI-Flash device (SST25VF040B). I am using Cube MX (4.19) to generate as much initialization code as possible.

So i have configured the SPI to Full Duplex Master mode with 8Bit Data Size, Motorola Frame Format.

The Problem i am facing is, that i can not read out consitend data from the flash device ( I am reading 20 Bytes in my example).

Erasing and writing the flash works fine but reading the data does not work. I checked the interface by connecting a logic analyzer (SALEA) to verify the SPI bus itself. What i see on the pin level looks perfect (see attachement), but the received data in the receive buffer ist corrupted. 

After that i set a breakpoint within the cube generated driver directly before the SPI DR-Register is read out. Doing that fixes the problem. Setting the breakpoint behind reading the DR-Register shows the problem. 

Finally i visited the Errata Sheet and found the paragraph 2.5.7 Packing Mode Limitation. (I am using Rev A Silicon)

And now the questions:

1. Do i really see the problem that is described in 2.5.7? Please let me know if you need more information to answere this question.

2. Is there a new Silicon Revision planed that fixes the problem? If yes, when will it be available?

3. Is there any way to avoid the packing mode? Maybe by changing the HAL driver code? 

4. I know that the current version of the CubeMX is 4.20. Is this problem fixed in that version?

5. Is there a patch (or something similar) available to fix this?

Any Help is highly appreciated

Thomas Jung

[Imen.D]

Posted on March 27, 2017 at 18:57

Hello

Jung.Thomas

,

The issue of SPI Packing modeis applicable forSTM32F030x8 devices with the device ID is 0x440 and for STM32F030x4/STM32F030x6 devices with the device ID is 0x444of the F0 exclusively (32K and 64K).

This issue is fixed at F0 versions with USB example.

The problem happens if user cannot guarantee to read received packed data out of the RxFIFO before just a half of a next packed data is received into this FIFO.Only workaround is to keep RxFIFO threshold at 8-bit and apply 8-bit read access of the SPI_DR register exclusively.

Hope this helps you.

Imen

[T J]

Posted on March 28, 2017 at 13:47

I use SPI extensively

if you cant read every byte its either too fast, try dropping the speed, or as you can see in the code here,

the Tx system is quite short, but Rx requires you to read the DR register again and again until it is showing empty.

then you have the last received byte and not some remnant from another transaction prior.

void SPI_2::write(uint8_t sendSPIByte){ 
while( !(hspi2.Instance->SR & SPI_FLAG_TXE));
*((__IO uint8_t *)&hspi2.Instance->DR) = sendSPIByte;
}

uint8_t SPI_2::read(uint8_t sendSPIByte){ 
while( !(hspi2.Instance->SR & SPI_FLAG_TXE));

*((__IO uint8_t *)&hspi2.Instance->DR) = TxSPIByte;// force the SPI to transceive 8 bit
while( !(hspi2.Instance->SR & SPI_FLAG_TXE));
while( (hspi2.Instance->SR & SPI_FLAG_BSY));
while( (hspi2.Instance->SR & SPI_FLAG_RXNE))
RxSPIByte1 = hspi2.Instance->DR;
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