SPI NSS cannot change automatically

[wenbin]

Posted on May 05, 2016 at 17:07

Hi, If I configure NSS as hardware management, it it controlled by the SPI peripheral. However, from the manual, the NSS is low when the SPI is enabled, and NSS is changed to high only when SPI is disabled.

I think it is a stupid design, it is nor compatible with many ICs. I have to configure NSS as software management. The NSS pin is configured as a general output IO, and control it manually (Low before transaction, High when transaction is completed).Experiment platform: STM32F746ZGT6 #spi

[Tesla DeLorean]

Posted on May 05, 2016 at 18:14

I think it is a stupid design

It is, the people designing it don't seem to be familiar with how the interface is used.

[wenbin]

Posted on May 06, 2016 at 11:17

I agree, I hope that ST may change the SPI design in the future!

[mikael2]

Posted on May 12, 2016 at 23:32

It is other chip designers doing it wrong. 

SS is active low see:https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

[Tesla DeLorean]

Posted on May 13, 2016 at 00:14

Yeah, I know, but the ST doesn't auto-magically transition it H-L and L-H in a manner that is remotely useful, or sufficiently flexibly, to allow its efficient use in any prevalent application of the bus. A general purpose solution would be able to handle the generally used cases, with ease, not with me disabling the peripheral and manually counting bytes, or to send the CRC.

It doesn't do this

https://upload.wikimedia.org/wikipedia/commons/thumb/6/6b/SPI_timing_diagram2.svg/400px-SPI_timing_diagram2.svg.png

If wikipedia is the threshold test, then sending a stream of 16 8-bit bytes does not transition SS on each byte.