2025-04-15 3:20 AM
I am trying to use SPI communication with the STM32H562 (for FPGA programming purposes).
The reference manual states that if SPI_CFG2's SSM = 1, the NSS can be toggled High/Low by switching the SSI bit in SPI_CR1.
However, the switching of SSI is not reflected in the oscilloscope observations.
Additionally, I tried setting the NSS port as GPIO instead of SPI communication and using HAL_WritePin to configure it, but this was also not reflected.
When using the NSS port for SPI, should I set the start register bits such as SPE and CSTART?
2025-04-15 3:27 AM
@Thoufiel wrote:The reference manual states that if SPI_CFG2's SSM = 1, the NSS can be toggled High/Low by switching the SSI bit in SPI_CR1.
No, that's not what it says:
2025-04-15 5:57 AM
In an SPI master, you can either use the NSS pin as SPI hardware-controlled, or you can configure it as GPIO.
If a slave, it should be hardware controlled.
> Additionally, I tried setting the NSS port as GPIO instead of SPI communication and using HAL_WritePin to configure it, but this was also not reflected.
Show relevant code and hardware setup. Controlling the pin as GPIO should be relatively simple exercise.
> When using the NSS port for SPI, should I set the start register bits such as SPE and CSTART?
Yes. The peripheral needs to be enabled in order for it to do anything.
2025-04-16 1:34 AM
Thank you for your reply.
I had read that section before my initial question, and regarding the content just before the red line,
I understood it as "Slave select can be performed by setting the SSI bit."
What does "internally" mean in this context?
2025-04-16 2:37 AM
I guess it means something internal (so, your software?) has to do it by manipulating the SSI bit ?
Perhaps @STTwo-32 could clarify ?
2025-04-16 5:45 AM
> I understood it as "Slave select can be performed by setting the SSI bit."
This is what it does, but the state is not reflected on the NSS pin. It's only internal. The NSS pin on a slave is an input anyway, wouldn't make sense to drive it.