spi frame

[simonsimon9172]

Posted on January 06, 2017 at 11:23

Looking at the STM32F7 , going to H7 when available.

Have some external peripherals that are SPI , but, need 24 bits of data in  a frame.

     i.e. the SPI CS goes active for 24 data bits, then in active at the end, CS must not rise during the transfer.

Looking at the SPI controllers, looks like they can handle up to 16 bits !

First thought was, lets us a gpio as the CS bit, and send out two frames.

Any thoughts on if this is the way, or can I trick the SPI controllers to generate a 24 bit spi stream,

Any thoughts on should I load the SPI as two 'words' of 12 bits, or one of 8 and one of 16 ?

   How would the FIFO on the SPI handle that.

Need a fairly fast speed here, and minimum CPU time, would like to 'send and forget'.

[waclawek.jan]

Posted on January 06, 2017 at 11:54

In I2S mode the data frame can be 24-bit, but the SS (WS/LRCLK) signal toggles between frames rather than pulses, which is probably not what you want.

Other solution is to generate both SCK and SS by other means (e.g. using timers) connect them externally to SPI pins and use the SPI as slave.

JW

[simonsimon9172]

Posted on January 06, 2017 at 13:37

Thanks.

Love the thought of ST making RF synthesizers, 

    I'll mention that to the FAE :>

re timers and speed. I'll have to have another look.

   With say a 16 bit SPI peripheral, I could use the FIFO on the SPI port. CPU sends data to SPI port, and forgets abotu it.

       With timers, I guess I'd be bit banging the data out, which sounds processor intensive and slow, 

Which was why I was asking , any thing I have missed here as an obvious faster solution ?

For reference, I have three of these things that need to be kept happy with data, 

    using the three SPI ports with the FIFO's I think is a way of doing, if it was not for the chip select issue at 24 bits. 

[simonsimon9172]

Posted on January 06, 2017 at 12:40

Thank you ,

   Your right, the chip select ( SS ) going up and down between the 24 bits of data is not good.

Using timers / GPIO is going to be a problem / slow generating SCK. Was rather liking the SPI at 35 Mb/s, and the FIFO's, send and forget. 

[waclawek.jan]

Posted on January 06, 2017 at 13:08

 Using timers / GPIO is going to be a problem / slow generating SCK.

I don't see why.

Was rather liking the SPI at 35 Mb/s, and the FIFO's, send and forget. 

I listed you the options I am aware of. ST surely will be happy to provide you with peripherals exactly fitting your needs, provided you buy enough chips.

JW

[Jeroen3]

Posted on January 06, 2017 at 15:10

Send 3 frames of 8 bits. This is the most suitable way, in which you still can use the DMA.

I don't think you can change the word size while active without penalty.

The other option is to use the DMA in bitband region and some timer. But I thought bitbanding was a feature in the core, and thus not available for the DMA. Can't find it in the manual though.

[waclawek.jan]

Posted on January 06, 2017 at 14:55

mulcock.andrew wrote:

       With timers, I guess I'd be bit banging the data out, which sounds processor intensive and slow, 

No. I did not say bit bang.

Other solution is to generate both SCK and SS by other means (e.g. using timers) connect them externally to SPI pins and use the SPI as slave.

JW

[simonsimon9172]

Posted on January 06, 2017 at 15:44

Thanks 

I'll have to think about how to use the timers to make SPI then, 

    any pointers please.

[simonsimon9172]

Posted on January 06, 2017 at 15:45

That makes sense , long day is al I can blame that on.

bitband, I'll have to look up,

Thanks