SPI DMA triggered by external GPIO event?

[ST User]

Hello,

I am trying to sample an ADC at high rate, and am looking for a way to avoid generating interrupts on every sample.

This ADC has a BUSY signal which indicates when conversion is in progress, so I can connect that to a GPIO and trigger off this signal by looking at the falling edge.

Is it possible to directly connect this falling edge trigger to start the DMA transfer without having to use an ISR? I haven't been able to find an answer in the documentation thus far.

I'm using an STM32H7, if it varies between configurations.

Thank you.

[waclawek.jan]

> Is it possible to directly connect this falling edge trigger to start the DMA transfer without having to use

> an ISR? I haven't been able to find an answer in the documentation thus far.

Not directly, but through timer. In "normal" STM32s, I mean.

The H7xxx is a different beast, I don't use it, I'd need to have a look. But at least the timer thing should work there too. Look at "Reception" in AN4666.

JW

[ST User]

Thank you, I'll take a look at that application note.

Since it seems like you can trigger the DMA with a timer, would it be easier just to have a timer channel in PWM mode (CHx CHxN), with one side (CHx) generating the "start conversion" signal to the ADC, and the negative (CHxN) generating the signal to the DMA to do the transfer?

Thanks again.

[Dave Nadler]

This is for an F4 family part but might be helpful:

https://community.st.com/s/question/0D50X00009q4MRTSA2/stmf4-external-interrupt-dma-20bit-spi-xfer-completion-interrupt-to-isr

[waclawek.jan]

One Compare channel has only one output from the compare circuitry, OCxRef, and that may be source of DMA request (trigger). It is then "forked" into two physical outputs, mutually inverted (and shifted by deadtime etc.).

But you can use several channels of one timer, one generating the start conversion and other generating a possibly phase-shifted request for DMA.

JW