SPI as master and FPGA as slave for some bits

[SMusc.1]

Hello everybody. I asking now for some help on my new project. On my stm32 u575zit-q i want send some bits, as master, on the FPGA EP2C5T144C8N as slave. This FPGA board is very simple (have no other peripherals on it). So i want send by means SPI, four bits in one pin of the FPGA. I know how write code for the SPI in stm32 using MOSI, CS, but now i am focused on SCK (serial clock) that the FPGA need to use for read some bit. I tried to found some on the web but i didnt. Have some one things to help me? On CUBE IDE i see the baude rate (Mbits/s for example set to 1 Mbit/s), but what aboout the SCK that the stm32 board transmit on the SPI pin? I have one idea of how i can implement and i share this with you: on CUBE IDE, if i knew the sck frequency, then i can set some check on my FPGA for read on the rising edge of the sck line, the data sending on the MOSI line of the STM32 board and load this value in some interna register of my FPGA to use it as I need later.

I hope that my issue is clear and say thank to all in advance.

[SMusc.1]

Okay easy. Now I will try to read in FPGA board, each clock period, the data send from stm32 board. Tks 

[Andrew Neil]

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@SMusc.1 wrote:

since my FPGA board is very simple, it have no SPI interface on it. For this reason i wanted know the sck frequency and not the data speed in Mbit/s.

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It seems you still haven't really understood how SPI works: exactly one bit is exchanged per clock cycle.

Therefore, the clock frequency (Hz)  is the data speed (bit/s).

[SMusc.1]

Andrew I really appreciate your support and that of all the members here in this community. Now that the relationship between SCK and bauderate is clear, on my FPGA I can connect one pin to stm32 SCK, one pin to CS and last to MOSI for half duplex comunication (witout MISO line). Now when I go to read the various bits in the code from the FPGA I will do it on the MOSI line, so I will see all the transitions of the bits. This of course I will do at every rising edge of the clock on the SCK line and the bits will be present instead on the MOSI line. So if I connect an oscilloscope on the SCK line output from the stm32 board I expect to see a signal with a frequency equal to the bauderate set in the cube IDE interface as in the attached image right?

[SofLit]

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@SMusc.1 wrote:

This of course I will do at every rising edge of the clock on the SCK line and the bits will be present instead on the MOSI line.

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That depends on the polarity you set: https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#/media/File:SPI_timing_diagram_CS.svg

[SMusc.1]

yes of course. Tks so much