SPI aberration (STM32F401VC)

[psdeering]

Posted on February 07, 2016 at 09:12

Hi all,

I have an issue with SPI on the STM32F401VC microcontroller.  What seems to be the problem is that the SPI device (SPI1) doesn't seem to drive the completion flags correctly on the hardware.  For example, I have setup SPI1 to transmit a single 8 bit test value (see attached hardware trace), and the BSY and RXNE are reporting that the transfer has completed and the byte received before it should be (see CS on the trace).  CS is being driven active before the SPI operation, and then immediately after the SPI transfer has completed.As can be seen in the trace, CS is being driven to DISABLE before the final clock cycle has completed, which shouldn't occur as the SPI transmit function is actively polling BSY and RXNE before CS is being set to DISABLE.Basically, the operation is to:     (1)  Drive CS low     (2)  Wait for TXE to become set     (3)  Write the byte to the data register     (4)  Wait for RXNE to become set     (5)  Retrieve the clocked in byte from the data register     (6)  Wait for the BSY flag to become reset     (7)  Drive CS high  Any ideas? 

[re.wolff9]

Posted on February 07, 2016 at 18:52Depending on the SPI ''mode'', the sampling of the MISO signal will happen on the up or down transition of the clock signal. In your trace it seems that the up-transition is significant. That ''finishes'' the transfer, and your input data becomes available (RXNE). If it works like this your software gets a better chance at getting the next data byte ready to prevent having to waste time leaving the SPI bus idle while you prepare the next byte. Worst case you can sample the SCLK output pin and wait for it to go low?

[Tesla DeLorean]

Posted on February 07, 2016 at 21:04

Step 2.5 : Read the data register to clear any pending RXNE, before outputting data