[solved]STM32F7 NOR memory with FMC

rmszal · ‎2015-09-07

Posted on September 07, 2015 at 11:34

Hello,

I have some problems with FMC when I try to port my code from SMT32F407(with FSMC interface) to new project based on STM32F746(with FMC). The only changes I've made are timings(adapted to 216 MHz clock) and init structures(FSMC => FMC).

I have also SRAM connected to the same data and address bus and it works well, so I think that my hardware is ok and problem is inside init code.

Thus, I have few questions: is there any difference between using FMC on STM32F4 and STM32F7? Should I change or add something in initialisation code when using FMC on STM32F7?

#nor-flash-fmc-stm32f7

rmszal · ‎2015-09-11

Posted on September 11, 2015 at 11:31

You were right. It looks like FMC address region belongs to 'External RAM', thus it is cacheable by default.

I solved problem by adding MPU region that covers NOR memory address, here is the code: http://pastebin.com/BdG6j1vL With this D-Cache can be enabled and it doesn't impact NOR memory.

I wonder why FMC_NOR example project from SMT32756G_EVAL works with enabled D-Cache and disabled MPU.

Thanks for clarification.

waclawek.jan · ‎2015-09-15

Posted on September 15, 2015 at 11:40

> I wonder why FMC_NOR example project from SMT32756G_EVAL works with enabled D-Cache and disabled MPU.

Can't this be because the example uses the memory only as a plain memory, whereas you attempted to read the ID, which means different data output by memory at the same address.

Memory mapped peripherals would present a similar ''hardware volatility'' problem.

JW

yada2 · ‎2015-12-17

Posted on December 17, 2015 at 23:48

Hello, is the cache enabled by default on FMC SRAM Bank 1 ? I am trying to port the FMC code used to interface with an ILI9325 LCD controller from STM32F4 to STM32F7. When doing a simple clear screen :

loop for 320x240 pixels :

*(data address 0x60020000) = color 0xFF00;

it seems some instructions aren't sent to the controller or aren't registered by the controller. Thus, only a third of the screen is cleared. Surprinsingly, adding a 1ms delay between instructions solves it. Changing SRAM Timing didn't help. Hardware is identical between both F4/F7 boards. Thank you.

waclawek.jan · ‎2015-12-17

Posted on December 18, 2015 at 08:56

Yes, this is the same problem as the original poster had. Use the MPU.

JW

AndyJT · ‎2015-12-22

Posted on December 22, 2015 at 12:29

I'd just like to thank everyone for their help on this subject.

I had the same issue with the NOR flash on the STM32F7 eval board (and am also wondering how the NOR examples work without setting the MPU)

In the end, all I had to do was call this to setup the MPU for the 128Mbit NOR Flash memory on the F7 Eval board:

static void MPU_Config(void)

{

MPU_Region_InitTypeDef MPU_InitStruct;

/* Disable the MPU */

HAL_MPU_Disable();

/* Configure the MPU attributes for 16Mb NOR Flash*/

MPU_InitStruct.Enable = MPU_REGION_ENABLE;

MPU_InitStruct.BaseAddress = 0x60000000;

MPU_InitStruct.Size = MPU_REGION_SIZE_16MB;

MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;

MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;

MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;

MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;

MPU_InitStruct.Number = MPU_REGION_NUMBER1;

MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;

MPU_InitStruct.SubRegionDisable = 0x00;

MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;

HAL_MPU_ConfigRegion(&MPU_InitStruct);

/* Enable the MPU */

HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

}