Single 0V GPIO Pulse Synched w/ Timer

[jvavra]

Posted on October 01, 2014 at 20:31

Using a STM32F427, I've got TIM5 generating an 8MHz PWM output. I've also got a GPIO output that is hooked to an active LOW enable on a device that needs to be turned on every once in awhile. What I'd like to do is, at the appropriate time in a simple superloop of code (i.e., non-RTOS), generate a single 0V pulse (2uS width) on the GPIO output (enabling the device), but synchronized with the next positive edge of the PWM output on TIM5. After the single low pulse, This would then be disabled until my next time through the superloop.

The 8MHz PWM generation is no problem. And I've got CH4 of TIM4 available on the GPIO output pin I want to use. Further, I don't use TIM4 for anything else. So I thought I could simply enable the peripheral clock for TIM4 when I want to generate the single pulse, then immediately disable it. But it doesn't seem to be working. I think I'm missing two parts:1) Is it possible to generate a negative pulse using the one-shot function that ST provides?  2) Leaving the periph clock for TIM4 disabled until I want this pulse SHOULD allow me fine control of enabling this single pulse, correct? If so, is it simply a matter of ensuring that I have a delay of at least (1/8MHz * 2) to ensure I can expect one, and only one, positive edge from the 8MHz PWM output? Or am I overthinking this and there's a much easier way to accomplish what I'm trying to do?Thanks!

[waclawek.jan]

Posted on October 02, 2014 at 11:03

> 1) Is it possible to generate a negative pulse using the one-shot function that ST provides? 

Yes. > 2) Leaving the periph clock for TIM4 disabled until I want this pulse SHOULD allow me fine control of enabling this single pulse, correct? Probably yes, but it's not the way how it is usually done, and I don't know if it may have some other unexpected consequences. Normally, one would configure the registers of timer to generate the pulse while keeping it disabled (CR1.CEN = 0), and then when the need for the pulse arises, just enable it, either through software, or, if the hardware permits (which in case of TIM5->TIM4 it does not), through chaining timers, the slave timer being set to trigger mode. > If so, is it simply a matter of ensuring that I have a delay of at least (1/8MHz * 2) to ensure I can expect one, and only one, positive edge from the 8MHz PWM output? I don't understand what do you mean by delay here. Please study the timer chapter in the user manual. JW

[jvavra]

Posted on October 02, 2014 at 14:24

Thanks for the reply. I've been over and over the manual, and am still struggling with #1. Any hints as to what register I should be looking at? All I see are configurations for which polarity to capture ON, not what the polarity of the pulse will be.

[waclawek.jan]

Posted on October 02, 2014 at 15:57

You are going to use the *compare* part of the capture-compare units, as that's what *outputs* signals. So you should read the ''output compare'' portions of the registers' description; also refer to Fig.161 of RM0090 rev.7. Output polarity is given by chosing one of the two PWM modes in OCyM bits of respective TIMx_CCMR1/CCMR2 register, and by setting/clearing the respective CCyP bit in TIMx_CCER register.

JW

[chen]

Posted on October 02, 2014 at 15:58

Hi

I think if you do not set TIMx_ARPE in TIMx_CR1 then, the counter will not load a value int tne TIMx_CNT reg when it reaches 0 (or the match value on count up) This effectively makes it a 1 shot counter/timer