Sensible Configuration for Timer Triggered Continuous STM32F4 ADC Sampling

[Seng Tak Goh]

Posted on March 15, 2018 at 15:35

Hi all,

I am about the configure the timer frequency which will trigger ADC to continuously scan and convert 5 channels. The callback will be from DMA.

The MCU I am using is STM32F407. System core clock is 168 Mhz. Fpclk1 = 42MHz, Fpclk2 = 84MHz...

A question came up when setting the ADC clock prescaler, and the overall configuration between the timer frequency and ADC settings. What would be the max or logical value?

My idea is as follow, please help to comment or correct me if I am wrong, without considering the external impedance.

I wanted to trigger the ADC every 84 kHz from a selected timer.

There are 5 channels to scan and convert in a row, 12 bit resolution and 15 sampling cycles for each channel.

Understanding from datasheet that typical fadc is 30 MHz, so does this mean that a sensible set of configuration would be limited by the following parameters:

1. Fadc prescaler should be >=4 ?
2. Timer frequency should be <= ( Fadc / ( channel_cnt * ( sample_cycle + conversion_cycle  )  )?

Thank you.

#timer-triggered-adc #stm32f407

[Pevy.Andy]

Posted on March 15, 2018 at 15:41

Something like this...

[Tesla DeLorean]

Posted on March 15, 2018 at 15:43

The more sensible solution is to use a TIM to pace the ADC, one can play games with the prescaler/sample time on the ADC side but fitting that manually is tedious, and a bit inflexible. The TIM's prescaler/period are integer which does provide for some headaches, but can usually be addressed by tuning the SYSCLK.

[Seng Tak Goh]

Posted on March 15, 2018 at 15:51

Hi Clive One,

I am getting a little more confused now. Please forgive my ignorance. My question arose when I am trying to use a TIM TRGO to pace the ADC sampling. So, TIM TRGO is set and ADC External Trigger Source and Enable bit are set accordingly..

If my understanding is right, that trigger pulse will only kick start the scanning and conversion, and the real process is still clocked by the ADC clock..

So my question point to a set of sensible setting which will not cause overlapping TIM triggering and not overclocking the ADC, while getting the max performance out of the two.

Thank you. 

[Pevy.Andy]

Posted on March 15, 2018 at 16:14

This is what my example does. I am using TIM15 to create a trigger for the ADC using the Update Event. This then causes the ADC to sequentially reads 2 channels and uses DMA to put the results in memory. After a number of the DMA sequences have happened I process the data.

[Seng Tak Goh]

Posted on March 15, 2018 at 18:08

Hi Andy, 

I know how to do this with Timer and ADC peripherals, my real question was the sensible TIM frequency and ADC prescaler values...