SDMMC trace length mismatch

[raghu tumati]

Posted on May 11, 2018 at 01:27

 Hi There

I was looking at AN4661, pg 45 where the signal routing guidelines for SDMMC is given. 

It has the below bullet points when it comes to skew 

• The skew being introduced into the clock system by unequal trace lengths and loads,

  minimize the board skew, keep the trace lengths equal between the data and clock.

• The maximum skew between data and clock should be below 250 ps @ 10mm

Now in an FR4 substrate, a general hand wavy calculations has 150ps for a 1inch (25.4mm) of mismatch between two lines. Going by this 250ps comes out to be 42mm of mismatch. 

So I do not understand what '250ps @ 10mm ' means? Can anyone explain? 

Also is 250ps @ 10mm specification for high speed mode or default mode. 

According to my understanding when SDIO operates at 50MHz, it called high speed mode and when running at 25MHz, its default mode. Correct me if I am wrong.  

I have not been able to get the clock running at using STM32F765VI with an SD card. The clock divider bypass option seems disabled for SD card mode. Is it available only for eMMC mode? 

With an SD card, am I limited to clock divider of 2. So it will always operate in default mode. Again, please correct me if I am wrong. 

Last question: Is there any similar guideline for layout for the DCMI interface? In terms of max tolerated Skew (trace mismatch between clk and data lines)? 

[Imen.D]

Posted on May 14, 2018 at 15:13

Hello

raghu_tumati

,

Please have a look to this application related to DCMI

http://www.st.com/content/ccc/resource/technical/document/application_note/group0/c0/ef/15/38/d1/d6/49/88/DM00373474/files/DM003734pdf/jcr:content/translations/en.DM003734pdf

: Digital Camera Interface (DCMI) on STM32 MCUs.

I will come back to you with the feedback about SDMMC questions.

Best Regards,

Imen.

[Imen.D]

Posted on May 14, 2018 at 18:01

Hi

raghu_tumati

,

I do not understand what '250ps @ 10mm ' means? Can anyone explain?

The maximum skew between data and clock should be below 250 ps @ 10mm. That means the maximum trace length difference between Data and clock should be below than 10mm (that equivalent in timing to 250ps of signal propagation on the trace).The maximum trace length should be below 120mm.

According to my understanding when SDIO operates at 50MHz, it called high speed mode and when running at 25MHz, its default mode. Correct me if I am wrong.

Yes, this is correct when SDIO operates at 50MHz, it called high speed mode and when running at 25MHz, its default mode. The clock bypass mode is available for both SD/and MMC cards.

We need to take care of the NEDGE bit when switching from default speed to high speed.

I have not been able to get the clock running at using STM32F765VI with an SD card. The clock divider bypass option seems disabled for SD card mode. Is it available only for eMMC mode?

No, in default mode, we can activate the bypass mode.

I hope that this brings some help to you.

Best Regards,

Imen

[raghu tumati]

Posted on May 14, 2018 at 19:11

Hi Imen

Thank you for the answer. 

But I am not sure I agree with the following statement you made. 

'

That means the maximum trace length difference between Data and clock should be below than 10mm (that equivalent in timing to 250ps of signal propagation on the trace)

'

In an FR4 (assuming a dielectric constant of 4.0) substrate the equivalent of 250ps of signal propogation time approximately 42mm and not 10mm? 

Am I wrong with my calculations? 

How did you guys come up with 250ps for 10mm?  

[raghu tumati]

Posted on May 14, 2018 at 19:36

Hi Imen

I have already looked a the AN5020 document. It has no mention of DCMI trace length and skew considerations in it. In fact there is no HW layout suggestions in the app note. Or atleast I could not find one? 

Can this information be found else where? 

[Tesla DeLorean]

Posted on May 15, 2018 at 00:02

>>

I have not been able to get the clock running at using STM32F765VI with an SD card.

What does that mean?

The SDIO/SDMMC peripheral can be clocked at rates greater than 50 MHz

BYPASS mode was problematic on some F4 parts. Pretty sure it works on the F7 at chip level, are you talking about issues with CubeMX?

>>

Is there any similar guideline for layout for the DCMI interface?

Lacking any specific guidance use some common sense for a parallel bus clocking at 54 MHz

[Imen.D]

Posted on May 15, 2018 at 11:56

Hello

raghu_tumati

,

You are right. Thedescription in theAN4661'should be below 250 ps @ 10mm' is confused.

After check, the maximum skew between data and clock should be between

60 and 100 ps @ 10mm depends on the design.

I raised this internally to update the application note according the new accuracy.

Thanks for bringing this to our attention.

Best Regards,

Imen

[raghu tumati]

Posted on May 15, 2018 at 18:32

Hi Clive

Thanks for the reply. Yes, I guess I am using cubeMX to set everything up. The datasheet mentions that SDMMC can be run at max clock of 50MHz (pg 45). 

So I setup my

SDMMCCLK

clock in cubeMX at 48MHz fed from the PLL48CLK. 

But in the settings of SDMMC in cubeMX, there is only an option for clock divider setting of zero. And from the formula 

SDMMC_CK = SDMMCCLK / [CLKDIV + 2]

I cannot see the option for clock bypass. 

Is this only cubeMX problem? So if I just set bit 10 (BYPASS) of  SDMMC_CLKCR, it should clock at 48MHz. 

I will try this soon and let you know. 

[raghu tumati]

Posted on May 15, 2018 at 18:33

Thank you Imen. That helps  

[liteyear]

Any progress here? Both the original text and this revision seem very confused. The app note hasn't changed.

Given the max speed of the SDMMC interface is 50MHz, perhaps this was supposed to read:

The maximum skew between data and clock should be below 250 mil.

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