2025-05-24 1:36 AM - last edited on 2025-05-24 2:02 AM by Andrew Neil
Hi,
I want to design my own LoRa-Board based on an STM32WLE-Chip. It is my first time handling with RF-related topics which is why I'm creating this post. I created a design which I would want to have reviewed for major flaws, so I can order my first prototype. I know that antenna impedance matching is not an exact science but I just want to correct the worst errors.
Where did I get the LC-Values from:
The LC-Values are according to AN5457 from ST (for 868MHz LoRa LowPower mode).
Where did I get the PCB-Antenna-Design from:
The PCB-Antenna-Design is from Design Note DN023 from Texas Instruments. However, the length of L6 is 2mm longer in my design in order to opimize the PCB-Antenna by shortening it.
What else did I take into consideration:
My questions:
I know it is a lot to ask but I would really appreciate if some of you reviewed my circuit and PCB-design so I can order my first version of it. All the relevant documents are in two .zip-files attached. Under "Resources.zip", you can find all the documents I referred to in my post and in "EndResult.zip", you can find my actual design.
Thanks in advance
Manuel
2025-06-27 7:19 AM
Hello @manuelambaum
I'm not a HW expert. But i think to verify your design, you should contact a RF HW expert. You can also refer to the reference designs mentioned on the table 2 of the DB4597. Also, I may recommend you follow the RF guidelines on this Mooc,the RF matching network design guide for STM32WL Series - Application note and the How to optimize the RF board layout for STM32WL5x/Ex MCUs - Application note.
Those resources should be helpful.
Best Regards.
STTwo-32
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