Reset timer on falling edge

con3 · ‎2017-11-08

Posted on November 09, 2017 at 05:29

Good morning everyone,

I'm using an stm32f772ze on a nucleof722ze dev board.

I'm not sure if this is possible, although I have read all the relevant documentation (I could have missed something) and I'm still unsure.

1) It seems like the timer reset mode is hard set to only be able to trigger on a rising edge, is there no way to reset the counter on the falling edge of an input signal?

2) The combined reset and trigger mode:

I set up the timer as follows:

Slave mode: Combined reset trigger mode
Trigger source:ETR1
Clock source: Internal
Channel 1: Input capture direct mode
With a periph-mem DMA triggered via TIM1_CH1

It seems like that when I use this mode, the counter just goes crazy and keeps running until a new edge is detected on the ETR1 pin and then just restarts and again counts like crazy. Doesn't this count the pulses that is received on the channel 1 input? it feels like in my application its counting the internal clock pulses as It counts even when the channel 1 input pin is floating or grounded.

Just to expand on what I'm trying to do:

I have a timer setup on input capture and a DMA transfer is triggered each time a rising edge is detected. Although I'd only like the DMA to be triggered for an x amount of times, lets say 96 times. So once the

trigger edge (ETR1)

has a falling edge, I'd like the DMA triggering to start for 96 clock cycles of channel 1 and then stop until another falling edge is detected on the trigger edge(ETR1) and have this continue until I end the process.

Any help or advice will really be appreciated.

#stm32f7-timer #stm32-f7 #dma-timer

S.Ma · ‎2017-11-08

Posted on November 09, 2017 at 07:38

Please clarify: 96 times means 96 falling edges capture in a 96x16 bit SRAM array?

Or the timer shall run for a time window of 96 timer clock cycle from trigger and stop when the time window is over?

Usually, I prefer to keep the timer rolling. If I want to get the timestamp for 96 falling edges, I keep the timer free running, use the DMA to store each capture into an array. When the DMA has completed the task (for example use a 2x bigger area with cyclical buffer DMA mode) as half full interrupt, backup the 96x16 bit data and use relative values:

Cap0 = (u16)TimCap[1] - (u16)TimCap[0]

Cap1 = (u16)TimCap[2] - (u16)TimCap[1]

Even if the timer overflows, the result will be correct.

The smoother the HW goes, the easier the debug.

con3 · ‎2017-11-09

Posted on November 09, 2017 at 08:58

Morning KIC,

What I mean is that I want to activate the timer via a trigger on ETR1 and have it do 96 DMA requests per the 96 falling edges it receives. So 96 bytes transferred to memory. After these 96 DMA requests, no further requests should be made to the DMA until another trigger is received on ETR1.

After the 96 requests the clock will continue to run onto the timer input capture pin and if these trigger DMA requests, the DMA will store useless data, which I want to avoid. Hence the trigger on ETR1 will tell the system when the data I want will be sent and these bits will always be 96 falling edges long.

con3 · ‎2017-11-09

Posted on November 09, 2017 at 20:47

Just to expand, If I can reset on a falling edge, all my problems are solved, so that's my biggest issue at this point