Relationship between ICache and ART of STM32F7

[dqi07234]

Posted on October 07, 2015 at 03:42

Hello experts,

I am working with STM32F7 Discovery board and STM32CubeF7. I made a small benchmark test and had found a stange phenomenon. It is about the relationship between ICache and ART Accelerator. Regarding instruction fetch form the flash, there are tow paths. One is the path which Flash-ART-ITCM-CPU. Another is the path which Flash-AXIM-CPU. When accessing ITCM area (i.e. address is 0x002xxxxx), I tried the following three options. 1) ICache is enable and ITCM is enable. 2) ICache is enable and ITCM is disable. 3) ICache is disable and ITCM is disable. The results were, 1) and 2) are almost the same execution time but 3) is twice later than 1) and 2). The execution time of 3) is almost the same as the case of fetching from AXIM area (i.e. address is 0x080xxxxx) on conditon ICache is disable. The results seems that ART Accelerator was not working. I guess ART would not work when ICache was disable. Is it true? Can anyone explain the reason? Thank you in advance and best regards, Yasuhiko Koumoto. #stm32f7-icache-art #smt32f7-ram-itcm-flash-itcm

[Nesrine M_O]

Posted on October 07, 2015 at 11:40

Hi Yasuhiko Koumoto,

I guess ART would not work when ICache was disable.Is it true?In fact The ART accelerator is available only for flash access on ITCM interface.When the code size of the user application fits into the internal Flash memory, the latter would be the best execution region either: – Through TCM (Flash-ITCM) by enabling the ART-accelerator  or– Through AXI/AHB by enabling the cache in order to reach 0-wait state at 216 MHzNote that the execution from Flash-ITCM/data in DTCM-RAM and Flash-AXI/data in DTCM-RAM have the same CoreMark score which is 5 CoreMark/MHz.I'd highly recommend you to have a look to the  

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00169764.pdf?s_searchtype=keyword

 application note: it provides a demonstration of the performance of the STM32F7 Series devices in various memory partitioning configurations (different code and data locations).-Syrine-

[dqi07234]

Posted on October 08, 2015 at 03:22

Hi  Syrine,

Thank you very much. I understood well. Also, the application note is very helpful. Best regards, Yasuhiko Koumoto.

[dqi07234]

Posted on October 10, 2015 at 01:10 Hello Syrine, I cannot understand the differences between Flash-ITCM and RAM-ITCM. What are they? My understanding is that Flash-ITCM is path Flash-ART-ITCM IF (via no ITCM RAM) and RAM-ITCM is ITCM RAM-ITCM IF. Also, Flash-ITCM can be accessed from address 0x00200000 and RAM-ITCM can be accessed from address 0x00000000. Is it correct? If it is correct, I have four questions. 1) How to initialize ITCM RAM? Should CPU put codes into ITCM RAM in advance? 2) If ITCM is enable and ART is disable, which path does instruction fetch from Flash-ITCM go along? In this case, from my experiment it seem to fetch codes from ITCM RAM. 3) Is ITCM RAM area fixed to from 0x00000000 to 0x00003FFF? 4) Is the vector table of STM32F7 located from 0x00200000? Thank you and best regards, Yasuhiko Koumoto

[Tesla DeLorean]

Posted on October 10, 2015 at 02:23

How can I put instruction codes into ITCM RAM and fetch from it?

memcpy() your code starting at 0x00000000, and jump to it? Create a linker script or scatter file that places the 0x00000000 16KB executable section within the FLASH load region, and have the C startup code automatically copy your routines there?

[dqi07234]

Posted on October 10, 2015 at 02:35

Hello clive1,

I'm sorry. I modified the previous questions after writing your answer.memcpy() your code starting at 0x00000000, and jump to it? Is this method valid? I did so and I got the diffrent execution time compared to execute from 0x002xxxxx. I came to have other questions now. Can you help me? Thank you and best regards, Yasuhiko Koumoto.