Reading of ADC jumps randomly by about -20 counts

[AWies.1]

I am currently using an STM32L475VCT in my board design, and I also have an STM32L476G-EVAL board.

I have ADC1 set up for sampling 6 channels continuously. Each conversion is triggered by an output from timer 1, I am also using 4x oversampling. The timer is running at 100kHz, the ADC clock frequency is 12MHz, sampling time 12.5 clk, so each conversion including oversampling takes about 8µs. With a static input signal, when I look at the conversion values, then I can see that sometimes the reading is about 20 counts lower, and this happens on all channels. It also happens on the internal voltage reference channel and the CPU temperature, so this effect can be seen on all channels. The same happens when I run the conversions continuously, so not triggered by the timer.

I see this effect on both the EVAL board and my own design. My own design is compatible with both an STM32L475VCT and STM32F103VCT. On the STM32F103VCT all values are stable, for the same setup of the ADC and timers, so I do not see this effect. My own design runs the microcontroller off 3.3V and uses an external voltage reference. All supply pins are well bypassed with dedicated capacitors.

What can cause this to happen?

[TDK]

Are you calibrating the ADC at startup? You seem to have everything else I can think of covered.

[AWies.1]

Yes, it is calibrated.

I also have a ADC2 set up for conversion of a single channel only, software triggered. As soon as I start conversions on ADC2, then I see the random jumps on ADC1. I tried to hardware trigger ADC2 with the same signal as ADC1, so both are pretty much converting synchronously, but I am still getting the jumps. I am at a loss what I can try next...

[AWies.1]

Further try and error showed that the channels for the CPU temperature and voltage reference are the ones mainly affected. I switched off oversampling, so that the conversion on these channels is guaranteed to be finished before the next trigger pulse arrives (with oversampling the total conversion time extended beyond that), and the issue seems to be reduced greatly. It feels like as if ADC1 does not like to be in the sampling phase when ADC2 starts a sampling / conversion.

[S.Ma]

Think of the adc as a short time discharged sampling cap recharching to input voltage. Vref and Vtemp need minimum sampling time. Have you tried 4x longer sampling, no averaging?

[AWies.1]

According to the data sheet the sampling time for Vref should be 4µs and for the CPU temperature 5µs. My code initializes the sampling time to 92.5 clk = 7.7µs, so there should not be an issue. I checked this by increasing the sampling time, and there was no change in behavior.

I like to stress that the issue only occurs when I start using ADC2. Without ADC2 all the data I get from ADC1 is stable. According to the description ADC1 and ADC2 are "closely coupled", so maybe there is an unexpected interplay. I think only an engineer from ST would be able to answer this. I also like to stress that with the same setup on an STM32F103, I do not see any effect on ADC1 when I start using ADC2. So this is an L4 series specific issue.

[Piranha]

"Ensure DEEPPWD=0, ADVREGEN=1 and that ADC voltage regulator startup time has elapsed."

Does your code wait for that time before starting the calibration?

[AWies.1]

I did all this, and as long as I only use a single ADC, everything is just fine.

I did a little bit more try-and-error investigation and found that the issue occurs if the sampling phase on the one ADC starts or ends while the other one is in the conversion phase. It feels like as if the reference voltage has a spike if this happens, and this screws up the conversion. I am using an external reference voltage, which is properly bypassed with a 10nF and a 1µF capacitor, as specified in the data sheet and application note. I also like to stress again that the issue happens on the EVAL-476G evaluation board (which hopefully is designed properly) and my own design, and the issue does not occur with an STM32F103. Evidently there is difference between the design of the ADCs of an F103 and the L475, and the design of the L475 is much more capricious than the F103. Note to ST: I am not impressed...

What helped me was getting the timing between the two ADC right. I am now triggering both ADCs from two different outputs of the same timer. I increased the sampling time on the first ADC, so the second ADC, which is running with a shorter sampling time, has finished the sampling and conversion before the sampling phase of the first ADC ends. I also made sure that the second ADC is not sampling or converting during the conversion phase of the first ADC. I also found that on the first ADC the stability is not affected if a full sampling and conversion cycle on the second ADC is completed during the sampling phase of the first one.