Question regarding power scale mode and frequencies in RM0431 and DS11853

[Zeron]

I'm working on a course and until now all my examples worked fine using HSI as the system clock. But now I'm trying to get an ST7735 screen attached to SPI to work. The screen screen seems to require its hexadecimal instructions bitwise and the parameters following the instruction to be the next bits right after the last bit of the instruction has been sent. In the mean time between sending instructions and data, switching of other pins seems to be required.

Because I'm working with seperate functions to send commands and data, which also take the switching of the other lines to their account, I assume the execution time required for exiting one function and starting the next one takes too many cycles between data and command and therefore causing a gap between the instruction and the subsequent data being sent over SPI to the LCD controller.

Enabling prefetch and the Art accelerator combined with configuring the PLL to run at 176 mHz and using this device as system clock seemed like the right thing to do for me in this particular case. However, I'm not absolutely sure wether or not I'm interpreting the information from the corresponding tables and chapters in the Reference manual and the Datasheet right.

Paragraph 3.3.2 "Read access latency" from RM0431

Paragraph 4.4.1 "PWR Power control register (PWR_CR1)" from RM0431

Table 16 "general operating conditions" from DS11853,

Table 17 "limitations depending on the operating power supply range" from DS11853

In paragraph 3.3.2 in the note above Table 15 I see:

when VOS[1:0] = 0x11 the maximum value of Fhclk is 180 mhz.

In paragraph 4.4.1 "PWR Power control register (PWR_CR1)" I found 0x11 stands for Scale 1.

In paragraph 4.4.1 I see that by configuring the VOS bits I can set the device to work at three different power scales, 1, 2 and 3. Regarding this note and PWR_CR1 description, scale 1 is presumably the required setting for my purpose.

From here on and up until further down the road I can only work on with assumptions, because the manual doens't provide me with the hooks required for me to make me sure of my case anymore. Not unless the required information lies in other chapters that are out of my reach of comprehending, just because I lack the theoretical background on the electronics part of the MCU.

Anyways, in table 15, right below the note I just mentioned I see four collumns showing wait states for four different voltage settings. I only see three power scale options, but I assume this might have to do with enabling and disabling the power regulator.

Well, now, The Table 16 from the product datasheet shows me:

1.2 V internal voltage on Vcap_1 and Vcap_2 pins.

power scale 3 max 1.20 v max 144 mHz no overdrive

power scale 2 max 1.32 v max 168 mHz no overdrive

power scale 1 max 1.40 v max 180 mHz no overdrive

Using just this information got me stuck for a while. Bacause table 15 in paragraph 3.3.2 "Read access latency" shows me

Voltage ranges 1.8v to 2.1v / 2.1v to 2.4v / 2.4v to 2.7v and 2.7v to 3.6v. Except for 1.8v to 2.1v 176mHz is found in the tree other collumns, every time corresponding to a different amount of wait states, 6, 7 or 8 wait states. I can't tell which one to choose. Besides that, the voltages in table 15 from the reference manual don't match the voltages described in table 16 from the product datasheet.

After this I decided to search for all occasions where I could find more information on Vcap_1 in the datasheet, but this didn't provide me the information required for moving on. I remained stuck until I accidentally scrolled down a bit to the next table in the product datasheet, table 17 "Limitations depending on the operating system power supply range" where I thought I found values that could somehow relate to the information I discussed before, however I didn't find any description regarding wether or not my assuptions are right. The operating power supply ranges VDD values in this table seemed to match the voltage ranges used in the header of Table 5 "The number of wait states according to CPU clock (HCLK) frequency."

After more closely inspecting the voltages mentioned in table 15 and comparing them to table 16 of the datasheet, I came up with the next theory.

is VDD equal to Vcap_1 plus Vcap_2?

This is the only thing I could come up with to get the different voltages described in the different tables to make sense to me.

If I'm right about this, I can move on and program the Flash latency to 7 wait states. This math seems logical to me, but I can find nothing in the manual that confirms these conclusions. I found no section that tells me for sure that I am right in interpreting these values.

I cannot find anywhere what voltages the VOS bits in PWR_CR1 relate to nor what power will come from what pins by changing the VOS power mode.

Neither can I find anything about VDD realy being related to Vcap_1 plus Vcap_2 in any sort of way, unless I have to retreive this information from the electro chart diagrams in the datasheet, but thats out of my league because I am a programmer and not an electronics engineer.

Is there anyone who can confirm wether or not I'm right here? The fact that this regards voltages I am a bit concerned of breaking the device, but I do want to move on. The relations between the different voltage levels and powerscales I described earlier on do seem to relate but I need to have this confirmed to be sure.

[TDK]

> is VDD equal to Vcap_1 plus Vcap_2?

No.

> Neither can I find anything about VDD realy being related to Vcap_1 plus Vcap_2 in any sort of way

They are not related in any way. The voltage on VCAP comes from an internal regulator. You should not be connecting anything to the VCAP pins apart from an appropriate capacitor.

At a programming level, you shouldn't be dealing with the VCAP voltage at all.

[Zeron]

Table 16 "General operating conditions" in the datasheet shows different frequencies and voltages being set by changing the VOS bits in PWR_CR1. I need to know the voltage to find the right Wait State in Table 5 "The number of wait states according to CPU clock (HCLK) frequency." in the reference manual.

Assuming the 1.20, 1.32 and 1.40 volts that I find in Table 16 "General operating conditions" is meant to be the output currency on Vcap_1 and Vcap_2, relates

Scale 3 to 144 mHz and 1.20v,

Scale 2 to 160 mHz and 1.32v and

Scale 1 to 180 mHz and 1.40v.

These voltages seem to be exactly half of VDD as shown in table 17 "Limitations depending on the operating system power supply range".

The VDD voltages that appear in this table exactly match the voltages shown in Table 5 "The number of wait states according to CPU clock (HCLK) frequency."

That is why I assume both pins, Vcap_1 and Vcap_2 both get 50% of VDD voltage. I found not other way to link the three power scales from the VOS bits to the four voltages in the header of Table 5 "The number of wait states according to CPU clock (HCLK) frequency." RM0431, to the power scale settings described in Table 16 "General operating conditions" in the datasheet.

Being able to link the voltage to the power scale is the only way I can find the right collumn in table 5 in the reference manual to determine the right number of wait states for prefetch. There is nothing in the reference manual, nor the datasheet that shows how these values correspond to one and other, so I have to keep assuming my findings are right.

[TDK]

The voltage in this table refers to VDD, not VCAP. VDD should not be an unknown in your design. If it changes, use the lowest voltage in the range. You can set the number of wait states higher than what the table shows, but not lower.

[Zeron]

I did some more research on the Datasheet by searching on V12, VDD and Voltage Regulator and found some more usefull information afterall.

V12 as mentioned in Table 16 "General operating conditions", the output on Vcap1 and Vcap2 stands for the internal digital voltage. As I found in Figure 27 "STM32F723xx power supply scheme" as well VDD as Vcap1 and Vcap2 are connected to the internal voltage regulater, but on seperate lines, so there is indeed no direct relationship between the currencies of both power lines except for being connected to the same voltage regulater, but on different outputs.

On page 123 of the datasheet below 'On-chip peripheral current consumption I found that "Scale mode 1 selected, internal digital voltage is 1.32", same as typical voltage in Table 16 "General operating conditions". For my math earlier on I took the max voltages from this table. Anyways, now I'm sure scale 1 is the highest currency for as well VDD as for the internal digital voltage V12 with regulator on and scale 3 the lowest. And that all is configured with the same VOS bits. I'm finally sure what collumn I need for the best performance results, I'm going to set the latency to 7 wait states, the most optimal number for this frequency and power scale.