Question about SDIO FIFO

[zeros_and_ones1991]

Posted on February 08, 2014 at 16:36

I made my own SDIO library and it is working fine , but I wanted to increase the transfer rate , so I read on the datasheet that the FIFO has 32 entry , while the KEIL defined only one FIFO register , so Are there really 32 FIFO places ? ...... or it is just 32 entryies to the same place? .

[ilmars]

Posted on February 08, 2014 at 20:00

I don't know about FIFO but if you care about data transfer rate, then better plan to use DMA.

[Tesla DeLorean]

Posted on February 08, 2014 at 20:26

Peripheral registers and latches generally don't look/behave like memory cells. There is lots of complicated logic, and inaccessible structures behind the scenes.

The FIFO has 128 bytes (32 * 32-bits) stacked behind the one memory location. The depth can be read via another register.SDIO with DMA can achieve speeds of the order 13-15 MBps, writes are often significantly slower, by SDHC cards come in a wide range of performance levels which dramatically alter performance.Also don't do single block/sector reads and writes, in order to achieve any level of performance you want to read/write multiple blocks, 32 KB being a reasonable sweet-spot for a transfer length vs command setup latency.

[zeros_and_ones1991]

Posted on February 08, 2014 at 21:28

thx Clive and Ogden , ...... Yes i 'm currently working on the DMA to transfer data between the SDHC card and FSMC external SRAM , to do processing on the data ....... I just wanted to know if i can load the whole 32 SDIO FIFO entry rather than what im doing now which is load only the SDIO first FIFO address (defined in the manual) and wait for the  RX/TX empty interrupt ? ...... because that way i would have reduced the transfer overhead .