I'm trying to interface the STM32F446RET6 with M95P32-IXCST/EF, a QuadSPI EEPROM. For the 64 pin STM32F446RET6 pin PB2 (pin 28) is used both as BOOT1 and QUADSPI_CLK
I don't see any other pins that can be used as QUADSPI_CLK for the 64 pin package. Is there a way to interface with the EEPROM?
Hello @S-Bat and welcome to the community,
As mentioned in the datasheet PB2 can be used for BOOT1 and for the QUADSPI_CLK.
Also note that this 64 pins package supports only single and dual transfer mode. Only QUADSPI_BK1_IO0 and QUADSPI_BK1_IO1 are available in this package.
If you want to transfer data in Quadspi mode, you might need to consider using a different package.
Thank you.
Kaouthar
Hi @KDJEM.1
I see that PB2 can be used for both BOOT1 and QuadSPI but I'm a little confused how it would impact the flashing process and how I should go about the schematic. I'm not sure I fully understand it, but if I only want to run user code (and not burn any new bootloader or something) that means booting from user flash
AN2606 says: "The STM32F446xx bootloader is activated by applying Pattern 1 (described in Table 2)"
First I'm confused exactly what is meant by "bootloader is activated", what boot mode does that refer to?
If BOOT1 pin needs to be 0 does that mean I need a pull-down resistor on the BOOT1 pin? Would that interfere with the same pin connected to the EEPROM during normal operation?
Hello @S-Bat,
First I'm confused exactly what is meant by "bootloader is activated", what boot mode does that refer to?
AN2606 STM32 microcontroller system memory boot mode. "bootloader is activated" means the system memory boot mode is enabled by applying pattern 1 configuration.
In STM32F446 MCUs, BOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been sampled, the corresponding GPIO pin is free and can be used for other purposes.
To activated the Main Flash memory boot mode, you need BOOT0=0.
The below figure shows the external connection required to select the boot memory of the STM32F4xxxx
Thank you.
Kaouthar
