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Processor crash on PG10 initialisation

GeertZelf
Associate III

Hi all,
I am in the process of bringing up a prototype board with a STM32L4R7ZIT6. I'm using CubeMX and use it for generating the startup code. I've configured a lot of peripherals.

When I configure PG10 as an input, the CPU crashes. Exactly at the moment that te confirmation is written in te control register of the io-port. When no other io's are configured, there is no problem. I tried to remove a lot of the peripherals, but the problem still exists. Is this a known issue? 

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Accepted Solutions
GeertZelf
Associate III

Problem solved.
Sorry for keeping you Buzzy. The PG10 has a capacitive coupling with the enable signal of the LDO. When the PG10 is configured as an output, it causes a smal glitch at the EN input, causing to power supply to drop for a short moment. Enough to have the CPU to restart. oeps...

Thank you all for your committment and involvement.

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17 REPLIES 17
AScha.3
Chief

>Is this a known issue? 

did you read the errata sheet of this chip?

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Crashes how exactly? Code / MCU ends up where?

Dying in silently in while(1) loops will tell you nothing externally. Instrument the Hard Fault and Error Handlers so you can get actionable data. Stop in the debugger, understand where it is and what it is doing.

Other PG pins working? VCCIO Enabled? EXTI or Interrupts? 

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Hi AScha.3,

Thank you for the tip. I checked it after your message. But no items on this issue, nor on my other issue. DAC via opamp 

Hi Tesla,
Thans for your rapid reply. i'll answer your questions below:

- The other PG pins are working PG 0 ~PG 6 are unsued, PG 7,8 for the LPUART, PG 9 ~PG 15 are digital inputs and outputs.
  Workin in this context means 'can be configurated and initialised' There is no software yet using these io's.

- VCCIO Enabled?: I donot know what that means. I did connect the VDDIO2 pins tot the 3.3V VCC power supply.
- EXTI and Interrupts are not (yet) used.

Stop being coy and post an .ioc or code.

On the L4+ the VDDIO2 on GPIOG bank must be explicitly enabled

    /* VddIO2 must be enabled to access GPIO port G[2:15] */
    __HAL_RCC_PWR_CLK_ENABLE();
    HAL_PWREx_EnableVddIO2();
    __HAL_RCC_GPIOG_CLK_ENABLE();

Is the configuration causing the MCU to RESET? Scope the NRESET/NRST pin, review other connectivity on a board level.

Stuck in Default_Handler ?

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

Hi David,

 

Thank you for your reply. I'd love to send my .ioc file. But the site refuses to accept it. 

GeertZelf_0-1700151568868.png

Has anyone a solution?

 

Thank you Tesla,
I'm sorry, but i cannot find how to enable the VCCIO on GPIOG bank. Could not find it in any manual. So a hint would be apreciated.

Regards,

Geert

AScha3_0-1700154872552.png

from p.  24/307  -> DS12023 Rev 5

AScha3_1-1700155151918.png

did you connect vddio2 -> vdd

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