Problems with JTAG

[anm]

Posted on May 14, 2009 at 09:12

Problems with JTAG

[anm]

Posted on May 17, 2011 at 13:10

Hi!

Today I got once the error: Wrong AHB ID (15:3). Expected 0x04770001 (mask 0xFFFFFF0F), Found 0x000000F0... But now, I get the same error as before... EDIT: The error with the wrong AHB ID occurs, when I put an oscilloscope at the reset pin!? EDIT2: The error occurs then as long, as I do not disconnect the power for a few minutes. [ This message was edited by: anm on 04-05-2009 15:48 ] [ This message was edited by: anm on 04-05-2009 16:14 ]

[rael]

Posted on May 17, 2011 at 13:10

This is speculative, but if your jtag behaviour was not consistent today, then perhaps it's your clock rates that are the issue.

Also, your ''Wrong AHB ID (15:3). Expected 0x04770001 (mask 0xFFFFFF0F), Found 0x000000F0... '' error appears to be indicating inverted hardware data from your device to the JTAG. It seems an unlikely error to get from any other source. Unless you are not programming the device the JTAG expects to see... i.e. wrong device selected, or incorrect device ID on the device (check errata) Still.. looking like a pin state inversion to me.

[anm]

Posted on May 17, 2011 at 13:10

Hi!

So I got another PCB - exactly the same behaviour. I exactly get the same error. If I disconnect the Pullups (see Schematics), I get the following: Could not find supported CPU on JTAG chain. Bad JTAG communication: Write to IR: Expected: 0x1, got 0x0 (TAP Command: 2) @ Off 0x5. Unable to halt ARM Core. @real: The device I've selected does not matter. I can select what I want, I always get the same error. And how could a pin state inversion could be? Thanks.

[anm]

Posted on May 17, 2011 at 13:10

Quote:

On 08-05-2009 at 14:48, Anonymous wrote: Sorry - are you certain that your JLINK still works correctly with your ''official'' Dev board? Yes - it still works propably there and I can program the controller on the devboard. Yesterday I tried my software for the controller on my board.

Quote:

If it works there - believe you must look @ the various JTAG signal levels @ the pins of STM32 - first on the Dev bd. and then on your new custom. (look especially hard @ Jtag clock pin) I will do this on this weekend - but someone hast taken the oszilloscope away from the laboratory 😉

Quote:

Finally - can you borrow another JTAG device? Believe that an independent confirmation of the error message will be helpful. I realize that these problems are maddening - anything you can do to gain understanding will help... Yes, I already tried another device - we have three of them here... With every device, I get the same error. I also tried without pull up/down, but this changed nothing without the value from 0xFFF... to 0x000...

Quote:

* Two add-on ideas: 1) Segger may better advise you: cause/correction of that strange error message. 2) Have you any ''extra'' signal routings on any of the JTAG pins? Something must be distorting and/or altering their levels... Segger already knows about the issue: http://www.segger2.com/index.php?page=Thread&threadID=323 But up to now they had no idea how to solve it. Thanks - and I will try to look at the JTAG signals in the next days.

[jj]

Posted on May 17, 2011 at 13:10

Sorry - are you certain that your JLINK still works correctly with your ''official'' Dev board?

If it works there - believe you must look @ the various JTAG signal levels @ the pins of STM32 - first on the Dev bd. and then on your new custom. (look especially hard @ Jtag clock pin) Finally - can you borrow another JTAG device? Believe that an independent confirmation of the error message will be helpful. I realize that these problems are maddening - anything you can do to gain understanding will help... * Two add-on ideas: 1) Segger may better advise you: cause/correction of that strange error message. 2) Have you any ''extra'' signal routings on any of the JTAG pins? Something must be distorting and/or altering their levels... [ This message was edited by: jj.sprague on 08-05-2009 14:53 ]

[jj]

Posted on May 17, 2011 at 13:10

Wow - looks like you've covered the majors.

Our forum friend ''lanchon'' once commented that the STM32's Jtag clock pin may have a ''different'' treatment than all other Jtag pins. (it may have internal ''pull-down'' - others all have pull-up. Forgive me - on the road - this from my memory while waiting to meet w/client) Suggest that you measure the values of ''each'' Jtag pull-up on the working board - then insure that those same values are used & routed correctly. Only thing we don't know is if your Jtag signals route to other components - which may cause distortion? Have you ohmed between Jtag pins - perhaps a ''board design'' short? If your scope ''disappeared'' to production/repair - we can just imagine what happens to your lab's tools...

[anm]

Posted on May 17, 2011 at 13:10

Quote:

On 08-05-2009 at 15:23, Anonymous wrote: Wow - looks like you've covered the majors. I hope so...

Quote:

Our forum friend ''lanchon'' once commented that the STM32's Jtag clock pin may have a ''different'' treatment than all other Jtag pins. (it may have internal ''pull-down'' - others all have pull-up. Forgive me - on the road - this from my memory while waiting to meet w/client) Yes - I have a pull down there...

Quote:

Suggest that you measure the values of ''each'' Jtag pull-up on the working board - then insure that those same values are used & routed correctly. I've done that - all correct 😉

Quote:

Only thing we don't know is if your Jtag signals route to other components - which may cause distortion? There is only the STM32F103.. in the chain, nothing else (see Schematics under

http://testaccount.ywh-server.info/schematics.pdf

, thats the whole board)

Quote:

Have you ohmed between Jtag pins - perhaps a ''board design'' short? I have also done this - all ok 🙂

Quote:

If your scope ''disappeared'' to production/repair - we can just imagine what happens to your lab's tools... I don't know what you mean, but this is a laboratory at an university - we have one digital scope - so a colleague of mine works with it 😉 So, now I go to ''work'' and tomorrow I will check the JTAG signals... I also found a documentation how the signals should look like - in the segger manual. Thanks and a nice weekend (my weeken will be full of debugging...)

[alex_ribe]

Posted on May 17, 2011 at 13:10

Hi:

Have you tried running the JTAG a a lower clock frequency (100KHz or less)? JTAG performance is somewhat dependent of the PCB layout, and one board might run at a higher JTAG clock than other. There is also the option of enabling the RTCK signal (see the J-Link setup window in your development system).This is used by JTAG to auto-negotiate the best clock speed to use. Regards, Alex

[jj]

Posted on May 17, 2011 at 13:10

Please check - - if you've installed a pull-down on Jtag clk and the STM32 also has internal pull down - you may not be able to drive the STM32 sufficiently high. (again - I'm out - have limited time/access)

Every non-STM32 we've designed ran correctly with ''pull-ups'' on each of the Jtag pins. IIRC - lanchon identified something different about one of the STM32's Jtag pins (believe this was the clock) Much earlier I did suggest that you slow the Jtag clock. Can't recall if you tried...

[16-32micros]

Posted on May 17, 2011 at 13:10

Hi,

In STM32 pull-ups and Pull-downs are already embedded internally to save extra resistors on your PCB , Please remove all external Pull-ups / Pull-downs , it should work perfectly. Internal pull-ups and Pull-down are in range of 40KOhm. Hope this helps you. Cheers, STOne-32.