Problems dividing HCLK - STM32L433RCTxP

[PMach.3]

Hi, everyone.

When implementing a sort of delay function using Timer2 to have a more precise time control, while putting the MCU in power-saving mode, I noticed that the division performed to the APB1/2 clocks does not correspond to what's programmed. See below a short description of what I observed:

RCC->CFGR |= (RCC_CFGR_PPRE1_DIV1 | RCC_CFGR_PPRE2_DIV1);    //No division, as expected
RCC->CFGR |= (RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2);    //No division, expected by 2
RCC->CFGR |= (RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV4);    //Divides HCLK by 2, expected by 4
RCC->CFGR |= (RCC_CFGR_PPRE1_DIV8 | RCC_CFGR_PPRE2_DIV8);    //Divides HCLK by 4, expected by 8

Meanwhile, I noticed that on the .ioc file the frequency at the output of the APB1 Prescaler gets multiplied by two if this prescaler is greater than 1 (2, 4, 8 or 16), as shown below.

I can't change the multiplier that outputs the clock to the APB1 timer clocks and, thus, I suspect that these might be related since it might explain what I observed.

Is that so? If, yes, what's the reason and/or can I find documentation regarding this topic?

Thanks in advance,

Pedro Machado

[TDK]

The reference manual will have details about the timer clocks. Sometimes hard to find if you don't know where to look, but here it is:

https://www.st.com/resource/en/reference_manual/rm0394-stm32l41xxx42xxx43xxx44xxx45xxx46xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

(6.2.14 in this manual)

[PMach.3]

Hi, thanks for your answer.

Actually, I was looking for something more detailed on why this happens.

[TDK]

Because that's how it was designed, I guess.

The hardware is capable of having a higher TIM frequency than APB frequency, but only if the prescaler is x2 or more. Having a higher TIM frequency is advantageous in a number of scenarios, as it gives finer control. So the silicon designers made it so the TIM frequency is higher when possible.