I changed the code to the following :
// Cfg USB OTG peripheral
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST);
CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST);
// Note that the STM32F411 supports OTG, but we will disable this and
// force device to operate as Host- or Device-only
// From [1]p.763
// 1. Program the following fields in the OTG_FS_GAHBCFG register:
// – Global interrupt mask bit GINTMSK = 1
// – RxFIFO non-empty (RXFLVL bit in OTG_FS_GINTSTS)
// – Periodic TxFIFO empty level
// 2. Program the following fields in the OTG_FS_GUSBCFG register:
// – HNP capable bit
// – SRP capable bit
// – FS timeout calibration field
// – USB turnaround time field
// 3. The software must unmask the following bits in the OTG_FS_GINTMSK
// register:
// - OTG interrupt mask
// - Mode mismatch interrupt mask
// 4. The software can read the CMOD bit in OTG_FS_GINTSTS to determine
// whether the OTG_FS controller is operating in host or device mode.
if (USB_role == USB_HOST) {
core_cfg.role = USB_role;
// [1]p.720 Support FS/LS only with 48MHz PHY clock
OTG_FS_HCFG = 0b00000101;
// (4) Host-only mode; setting this bit requires 25ms delay [1]p.703
ATOMIC_SET_BIT(OTG_FS_GUSBCFG, OTG_FHMOD);
USB_Delay_ms(25);
// [1]p.707 The application must clear the OTG_FS_GINTSTS register at
// initialization before unmasking the interrupt bit to avoid any
// interrupts generated prior to initialization. The clearable bits
// are write-1, the remainder must be kept at reset value 0x0400 0020
//OTG_FS_GINTSTS |= OTG_HOST_ONLY_IRQs;
// Note that many ARM chips will take longer than 1 instruction cycle
// to clear an interrupt, leading to some false positives
while (USB_TRUE) {
ATOMIC_SET_BIT(OTG_FS_GINTSTS, OTG_HOST_CLEARABLE_IRQs);
reg_value = OTG_FS_GINTSTS;
if ((reg_value & OTG_HOST_CLEARABLE_IRQs) == 0x00) {
break;
} // end if
} // end while
// (1)
SET_BIT(OTG_FS_GAHBCFG, OTG_GINTMSK);
SET_BIT(OTG_FS_GAHBCFG, OTG_PTXFELVL);
SET_BIT(OTG_FS_GAHBCFG, OTG_TXFELVL);
// (2)
CLEAR_BIT(OTG_FS_GUSBCFG, OTG_HNPCAP);
CLEAR_BIT(OTG_FS_GUSBCFG, OTG_SRPCAP);
// [1]p.704 Table 132 (device only)
//MODIFY_REG(OTG_FS_GUSBCFG, OTG_TRDT_MASK, (0x08 << OTG_TRDT_POS));
// [1]p.704
MODIFY_REG(OTG_FS_GUSBCFG, OTG_TOCAL_MASK, (0x10 << OTG_TOCAL_POS));
// (3)
SET_BIT(OTG_FS_GINTMSK, OTG_OTGINT);
SET_BIT(OTG_FS_GINTMSK, OTG_MMISM);
// Note : The ST description above doesn't tell you to unmask the
// host port IRQ, so the device attach IRQ won't trigger the USB IRQ
SET_BIT(OTG_FS_GINTMSK, OTG_PRTIM);
// ...end ST host port enable description
SET_BIT(OTG_FS_HPRT, OTG_PPWR);
} // end if
At the end of executing this code, reg_value is 0x04000020, so it's still not clear to me why CMOD is not reflected here as the debugger view shows it being high. GINTSTS has the value 0x14000029 which corresponds to the following bits being HIGH : CMOD, SOF, NPTXFE, PTXFE, CIDSCHG. Since none of these are masked, it solves the problem of immediately branching to the USB ISR, but now when I plug something in to the USB connection the PCDET IRQ in FS_HPRT doesn't go off even though it was before. So I'm going to have to do additional research on how the USB peripheral is meant to be configured for hosting.
@waclawek.janI verified that all IRQs I'm attempting to clear when I write to GINSTS are host-accessible. The description for OTG_FS_HCFG says "This register configures the core after power-on. Do not make changes to this register after initializing the host." But it's not clear to me what "initializing the host" counts as. I moved this line up to come before setting the bit to force host-only mode and one or both of these changes seems to have finally stopped MMIS from going off, but I still can't detect device attachment as described.
@FBLGiven that CMOD is not an IRQ bit it's not clear to me why this always appears to read zero when I read GINTSTS. Right now the hardware setup consists of a Nucleo-F411RE board modified to have an 8MHz crystal on the HSE input and a breakout USB cable wired up to PA12/11. We don't have a sniffer so I can't record any actual USB traffic. Given that PCDET isn't going off when I plug something up and I can't start the enumeration process there is no traffic anyway.
