1 ACCEPTED SOLUTION
Accepted Solutions
As @waclawek.jan said, the DMA transfer complete indicates that the DMA is done, which will be before the peripheral has finished the output. Some peripherals do have extra flags for that, like TXE vs. TC flags in USART. But I don't see this for DAC.
I can confirm @MBertocchi observations like when transferring a 16-step sawtooth using circular DMA:
orange is the DAC output, blue a GPIO/LED toggled in the interrupt.
The code is at register-level, no HAL involved:
#include <math.h>
#include <stm32l432xx.h>
#include <sysclk.h>
// PA4 --> DAC1_OUT1
// PA5 --> DAC1_OUT2
// TIM --> DMA2 Ch 4 Select 3 --> DAC Ch 1
// TIM --> DMA2 Ch 5 Select 3 --> DAC Ch 2
// 17.4.6 DAC trigger selection Table 75.: TIM6_TRGO == TSEL 000
// 100 kHz sample rate
#define Fsample 100000
#define DAC_BUFFER_SAMPLES 16
uint16_t bufferL[DAC_BUFFER_SAMPLES];
// int the user LED at pin PB3.
void init_LED(void)
{
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOBEN; // enable clock for peripheral component GPIOB
(void)RCC->AHB2ENR; // ensure that the last write command finished and the clock is on
// set pin to output mode (1). Reset defaults for other registers are okay here
GPIOB->MODER = (GPIOB->MODER & ~GPIO_MODER_MODE3_Msk) | (1 << GPIO_MODER_MODE3_Pos);
}
void init_TIM6(void)
{
RCC->APB1ENR1 |= RCC_APB1ENR1_TIM6EN; // enable peripheral clock
(void)RCC->APB1ENR1; // ensure that the last write command finished and the clock is on
// PSC[15:0] Prescaler register - divides the counter clock by factor PSC+1. (reset value: 0x0000)
TIM6->PSC = 0;
TIM6->ARR = (SystemCoreClock / Fsample) - 1;
TIM6->EGR = TIM_EGR_UG;
TIM6->CR2 = (TIM6->CR2 & ~TIM_CR2_MMS_Msk) | (2 << TIM_CR2_MMS_Pos); // The update event is selected as trigger output (TRGO)
TIM6->CR1 |= TIM_CR1_CEN; // enable the timer (start counting)
}
void init_DAC1(void)
{
// DAC out are additional functions, no need to change reset defaults for GPIO
RCC->APB1ENR1 |= RCC_APB1ENR1_DAC1EN; // enable peripheral clock
(void)RCC->APB1ENR1; // ensure that the last write command finished and the clock is on
// DAC1 MCR MODE2[2:0] shall be reset default (0000)): Channel is connected to external pin with Buffer enabled
DAC1->CR = 0 << DAC_CR_TSEL1_Pos; // TIM6_TRGO (reset default)
DAC1->CR |= DAC_CR_TEN1; // trigger enable
DAC1->CR |= DAC_CR_DMAEN1; // DMA enable
DAC1->CR |= DAC_CR_EN1; // channel enable
}
void DMA2_CH4_IRQHandler(void)
{
if (DMA2->ISR & DMA_ISR_HTIF4)
{
DMA2->IFCR = DMA_IFCR_CHTIF4;
GPIOB->BSRR = GPIO_BSRR_BR3;
}
if (DMA2->ISR & DMA_ISR_TCIF4)
{
DMA2->IFCR = DMA_IFCR_CTCIF4;
GPIOB->BSRR = GPIO_BSRR_BS3;
}
}
void init_DMA(void)
{
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
(void)RCC->AHB1ENR;
DMA2_Channel4->CCR &= ~DMA_CCR_EN;
// DAC1 Ch1 trigger is DMA2 Channel 4 select 3, see ref.man. Table 41.
DMA2_CSELR->CSELR = (DMA2_CSELR->CSELR & ~DMA_CSELR_C4S_Msk) | (3 << DMA_CSELR_C4S_Pos);
DMA2_Channel4->CCR = 0; // disable channel for setup
DMA2_Channel4->CMAR = (uint32_t)bufferL;
DMA2_Channel4->CPAR = (uint32_t)&DAC1->DHR12R1;
DMA2_Channel4->CNDTR = (uint32_t)DAC_BUFFER_SAMPLES;
DMA2_Channel4->CCR = DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_CIRC | (1 << DMA_CCR_MSIZE_Pos) | (1 << DMA_CCR_PSIZE_Pos) | DMA_CCR_HTIE | DMA_CCR_TCIE | DMA_CCR_EN;
NVIC_EnableIRQ(DMA2_Channel4_IRQn);
}
int main(void)
{
sysclk_init_hsi_80();
for(int i=0; i<DAC_BUFFER_SAMPLES; ++i) {
bufferL[i] = 200 + 200 * i;
}
init_LED();
init_DAC1();
init_DMA();
init_TIM6();
/* Loop forever */
for (;;)
;
}
hth
KnarfB
