Problem or feature? ADC clock prescale is set wrongly in generated code for STM32H7743ZITx by STMCube FW V1-9.0

[HWhit.1]

I developing an application where I need to use 14 bit ADC sampling at 2 MS/s. This needs a fast ADC clock speed. I am using a V version chip that has a built-in /2 divider on the ADC clock. When I upgraded to STMCube FW V1-9.0 the other week, the code prodused defaulted to "Asyncrnous clock mode divided by two. The code produced was  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; This gave a net division by 4 yielding a ADC clock frequency of 10 MHz which crippled my application. In previous versions it was divided by 1.

Workaround: Manually edit the line inthe generated code to: "hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;

I am aware the early chip versions did not have the built in /2 prescaler. As this/2 prescaler is central to ADC set-up, it might be a good idea to make two version of the FW for the differenet chip versions.

Regards,

Harry J. Whitlow

[TDK]

The prescaler can be adjusted how you want in CubeMX with the Clock Prescaler field. Are you saying the default should be DIV1? Or that you can't change it to DIV1 in CubeMX?

I had no problem with doing this on a new project.

> STM32H7743ZITx 

Guessing this was meant to be STM32H743ZITx

[HWhit.1]

Hi,

In CubeMX I am unable to select the DIV1 option. I can change it to DIV1 only by manually editing the generated code. This is it bit tedious as I have a complex set-up in CubeMX. The "STM32H7743ZITx" should of course be "STM32H743ZITx".

Regards,

H.

[TDK]

No such problem here:

 

Attach your IOC if you can. Could be an issue with a converted project.

[Georgy Moshkin]

Check if​ rev.V option is selected. Revision selection list is somewhere in System core settings of STM32Cube configuration tool.

[HWhit.1]

Hi,

Thanks for the suggstion. I looked but did not manage to find the rev. V option in the System core settings. Maybe I am looking in the wrong place

I am using:

STM32CubeIDE

Version: 1.7.0

Build: 10852_20210715_0634 (UTC)

OS: Windows 10, v.10.0, x86_64 / win32

Java version: 11.0.10

with Firmware package:

STM32 FW_H7 V.1.9.0

I have uploaded the .ioc file. This has been through several STM32CubeIDE and firmware upgrades.

Regards,

H.

[TDK]

CubeMX will tell you the problem if you hover over what is grayed out.

 

The datasheet specifies a max ADC clock of 36 MHz, provided BOOST=1.

 

Since your ADC input clock is 40 MHz, a divider of /1 would violate this.

Your project has BOOST=0.

If you want max ADC clock, set BOOST=1 by selecting voltage scale 0, the change your ADC input clock to 36 MHz, then select the /1 divider.

[HWhit.1]

Thanks Everybody ! - this solved the problem and I can now set the DIV1.

For the rev. V chips the changes from rev. Y are detailed in AN5312 Application note Migration from RevY to RevV for STM32H743/753 and STM32H750 Value line microcontrollers. So as I am using a rev. V chip 40 MHz input clock will give a 20 MHz ADC clock.

Regards,

H.

[Georgy Moshkin]

System core → RCC → System parameters  → Product revision

[HWhit.1]

Thanks
H.

Harry J Whitlow
h_j_whitlow@hotmail.com