possible silicon errata on TIMx capture/compare prescalers

[jeff239955_stm1]

Posted on July 18, 2008 at 11:32

possible silicon errata on TIMx capture/compare prescalers

[jeff239955_stm1]

Posted on May 17, 2011 at 12:39

It appears there may be a silicon errata with the TIMx capture/compare prescalers which precede the four capture/compare registers in the TIMx timers.

Setting the prescaler to divided by 1 works. Setting the prescaler to divided by 2, 4, or 8 does not work.I have tested the prescalers using two independent example programs. Example one is an example I wrote (which does not use the STM32 library) and example two is TIM_Example6. To reproduce the problem, TIM_Example6 > main.c, change:

Code:

TIM_ICInitStructure.TIM_ICMode = TIM_ICMode_PWMI; TIM_ICInitStructure.TIM_Channel = TIM_Channel_2; TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1; TIM_ICInitStructure.TIM_ICFilter = 0x0; to

Code:

TIM_ICInitStructure.TIM_ICMode = TIM_ICMode_PWMI; TIM_ICInitStructure.TIM_Channel = TIM_Channel_2; TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising; TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI; TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV8; TIM_ICInitStructure.TIM_ICFilter = 0x0; Setting the prescaler to eight should divide the external clock frequency connected to PA.1 by eight (frequency in Hz is stored in the Frequency variable). However this is not the case. Instead, the frequency as read by the Frequency variable is not divided by eight and remains equal to the external clock frequency. For example, using TIM_ICPSC_DIV8 and a 1kHz clock applied to PA.1, the Frequency variable should store 125 (1kHz/8=125Hz). Instead the Frequency variable stores 1000. Can anyone comment or confirm/disconfirm if this divide by 1 being the only working prescaler setting is an undiscovered errata?

[jeff239955_stm1]

Posted on May 17, 2011 at 12:39

I forgot to say that examining the TIMx_CCMR2 register confirms the prescaler is correctly set as eight (that is the IC2PSC bits are 11).

Code:

Bits 3:2 IC1PSC: Input Capture 1 Prescaler. This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input. 01: capture is done once every 2 events. 10: capture is done once every 4 events. 11: capture is done once every 8 events.

[lanchon]

Posted on May 17, 2011 at 12:39

> using TIM_ICPSC_DIV8 and a 1kHz clock applied to PA.1, the Frequency variable should store 125 (1kHz/8=125Hz). Instead the Frequency variable stores 1000.

that's not correct. I don't know whether the CC prescalers work, but assuming they do the prediction is still that the variable should be set at 1000. as you can see in figure 95, the trigger input TI1F_ED comes directly from the edge detector and not from the CC prescaler, so the counter is being reset at 1000Hz and, though only one cycle in eight is actually being captured, the captured value should imply a frequency of 1000Hz. so the frequency variable should be updated at 125Hz with the value 1000. EDIT: TI1FP1 is used to reset the counter, not TI1F_ED. [ This message was edited by: lanchon on 13-07-2008 08:40 ]

[jeff239955_stm1]

Posted on May 17, 2011 at 12:39

In trying to digest what you are saying lanchon. I am studying Figure 120 and from the figure, I would envision 1000 Hz clock applied to TI1 producing a 1000 Hz clock on TI1F_Rising, then going into the divider with one rising edge coming out for every eight rising edges going in. You are saying this is not correct then? Can elaborate on what you mean by the counter being reset? Do you mean the divider being reset referring to the figure?

[ This message was edited by: jeff.heiss on 13-07-2008 08:29 ]

[lanchon]

Posted on May 17, 2011 at 12:39

> I would envision 1000 Hz clock applied to TI1 producing a 1000 Hz clock on TI1F_Rising

correct > then going into the divider with one rising edge coming out for every eight rising edges going in correct, this means that the capture is done at 125Hz, or each 8ms. however, between consecutive captures the timer will be reset 8 times, at 1ms intervals. so each time you do the capture (and a simultaneous reset), you'll read a capture value corresponding to the period between last reset and capture. this is 1ms, and that's why the frequency variable will be set at 1000. the reset comes from the TI1FP1 line (not the TI1F_ED, sorry my mistake) going through the slave mode controller (figure 95). the reset is not CC-prescaled, and that's the ''problem''. from 13.3.6 PWM input mode: - Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). - Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. these settings cause the 1ms periodic reset and make frequency measurement possible.

[jeff239955_stm1]

Posted on May 17, 2011 at 12:39

Sorry lanchon, I did not see TI1F_ED. However in my example program this signal is not used nor is CH1 being used, instead the external clock is applied to CH4. I am observing that CC4I in Figure 95 is being triggered at a rate of 1000 Hz using a prescaler of 1. However, changing the prescaler to eight should (I would think) cause CC4I to be triggered at a rate 125Hz. Instead it is still triggered at 1000 Hz.

The timer just loops indefinitely from 0 to 65535. No PWM mode is used. [ This message was edited by: jeff.heiss on 13-07-2008 08:55 ]

[lanchon]

Posted on May 17, 2011 at 12:39

let me clarify: I'm not saying the CC prescalers work, I wouldn't know, I'm just saying that there's no posted evidence here implying that they don't.

[lanchon]

Posted on May 17, 2011 at 12:39

jeff, I can't say anything about your other code for I haven't seen it. but regarding your modified example 6, it should be clear that the freq variable should be set at 1000 (just like it's being set), and that there's no reason to say that CC prescalers aren't working based on what you observe. if you don't agree with this, I can explain further. but I really can't help you with your non-disclosed code.

[jeff239955_stm1]

Posted on May 17, 2011 at 12:39

Code:

<BR>// called for every CC4I trigger <BR>void TIM2_IRQHandler(void) <BR>{ <BR> static u32 CH4_last; <BR> P = TIM2_CCR4 - CH4_last; <BR> CH4_last = TIM2_CCR4; <BR>} <BR>

Code:

<BR>// capture/compare prescaler CH4 is 8 <BR>// connect TI4 to IC4 (Figure 95) <BR>TIM2_CCMR2_INPUT_CAPTURE_MODE = (3 << TIM2_CCMR2_INPUT_CAPTURE_MODE_IC4PSC) <BR> | (1 << TIM2_CCMR2_INPUT_CAPTURE_MODE_CC4S); <BR> <BR>// enable CH4 interrupt (TIM2_IRQHandler called on CC4I trigger (Figure 95) <BR>TIM2_CCER = (1 << TIM2_CCER_CC4E); <BR> <BR>// enable CH4 capture <BR>TIM2_DIER = (1 << TIM2_DIER_CC4IE_BIT) <BR> <BR>// timer frequency = 1MHz <BR>/ 74MHz/7400 = 1MHz <BR>TIM2_PSC = 7400; <BR> <BR>// TIM2 count up <BR>// TIM2 rolls over to zero then starts again <BR>// enable timer <BR>TIM2_CR1 = 1; <BR> <BR>// slave mode controller unused <BR>TIM2_CR2 = 0; <BR>

Sorry, now I understand your explanation concerning TIM_Example6. Sorry I did not get it earlier. The problem is the behavior I'm seeing is still apparent in my test example. Prescaler set to 1: 1000 Hz input clock = 1ms 1ms * 1 MHz = 1000 P equals 1000, correct Prescaler set to 8 1000/8 Hz = 4ms 4ms * 1 MHz = 250 P equals 1000, incorrect. Should equal 250. This seems to indicated the prescaler is stuck to 1 even though is set as 8 in the TIM2_CCMR2_INPUT_CAPTURE_MODE register. [ This message was edited by: jeff.heiss on 13-07-2008 09:53 ]