disable interrupts

[fortunat2]

Posted on July 13, 2008 at 06:12

disable interrupts

[fortunat2]

Posted on May 17, 2011 at 12:39

I am working on a interrupt USART driver with interrupt driven receiving and transmitting.

It seems that I have a problem with mutual exclusion between main programm and interrupt handler. I use IAR EWARM tool chain and I don't know which routine I should use to globally disable/enable the interrupts. I am not familiar with the new interupt system of the Cortex M3 core. I would appreciate any suggestion which functions to use for this purpose.

[disirio]

Posted on May 17, 2011 at 12:39

I suggest to do it using inline assembler instructions, it is the most efficient way. I don't know how asm inlining it is done using IAR, I usually use GCC.

You may use the ''cpsid i'' instruction in order to disable interrupts and ''cpsie i'' to enable them again. Another option is to modify the BASEPRI register with the ''msr'' instruction in order to modify the minimum serviceable interrupt priority. regards, Giovanni --- ChibiOS/RT

http://chibios.sourceforge.net

[jilisegiar]

Posted on May 17, 2011 at 12:39

Hi,

The following example may help you:(see the stm32f10x_it.c file) FWLib/examples/USART/Interrupt It is available at following address:

http://www.st.com/mcu/modules.php?name=mcu&file=familiesdocs&FAM=110#Firmware

Rgds

[lanchon]

Posted on May 17, 2011 at 12:39

there are functions in the fw-lib for that. you can also disable the specific interrupts (but watch out for deadlocks). note that when a write goes though an AHB/APB bridge, it can reach the peripheral after the CPU write instruction has ended. so you can receive an interrupt after you disable it. after writing, read the same peripheral register to synchronize the CPU.

[fortunat2]

Posted on May 17, 2011 at 12:39

Quote:

On 11-07-2008 at 14:08, Anonymous wrote: I suggest to do it using inline assembler instructions, it is the most efficient way. I don't know how asm inlining it is done using IAR, I usually use GCC. You may use the ''cpsid i'' instruction in order to disable interrupts and ''cpsie i'' to enable them again. Another option is to modify the BASEPRI register with the ''msr'' instruction in order to modify the minimum serviceable interrupt priority. regards, Giovanni --- ChibiOS/RT

http://chibios.sourceforge.net

Hi Giovanni Thank you for your information I entered the instruction ''cpsid i'' in my code and I set a breakpoint after this instruction. My debugger (IAR / J-Link ARM) showed the following values for: PRIMASK: 0x00000000 CONTROL: 0x00000000 It seems that the ''cpsid i'' instruction had no effect and didn't set bit 0 of PRIMASK to 1 to disable the interrupt. But I am not sure if I can trust the debbuger for these special registers. Regrads Fortunat

[fortunat2]

Posted on May 17, 2011 at 12:39

I finally found the problem in my interrupt handler. There was a silly race condition. The IAR J-Link ARM-Debugger was missleading a little bit, because it doesn't show the state of the PRIMASK register correctly.

Regards Fortunat