PLL Maximum input jitter

[Bastien LS]

What exacly is the maximum acceptable jitter for the input reference clock ?

The chip we are using is the STM32U585QIIx. We consider using an external clock from a VCO as HSE, and increase the frequency of the clock using the internal PLL. The VCO is a part of a synchronisation loop.

[waclawek.jan]

I don't think the PLL would have any substantial problem with jittery input, as long as it's frequency remains within specs. Of course the input jitter will impact it's output jitter too.

JW

[Bastien LS]

Is not there a possibility for the PLL to lose the lock if the input signal is not stable ?

[waclawek.jan]

Define "lock".

PLL divides output from its VCO by N and compares the resulting edge with input signal edge, depending on whether it leads or lags it adjusts the VCO's control voltage through a filter. Now that filter of course can be designed in many ways and the particular details are mostly trade secrets, but most of the time it's relatively simple and straightforward - there's not much space on a chip to get fancy. In case of total loss of input signal the VCO will drift to some of its extreme (in 'F4 into minimum, but PLL's vastly differ between families), you can easily observe the rate of that drift to get a rough picture of how the filter behaves; and that in turn gives you a picture of how would it behave in case of jittery input.

Note, that I am not ST. This is a primarily user-driven forum with casual ST participance. If you want more, contact ST directly, through your FAE or web support form.

JW

[Bastien LS]

Thank you for your answers.

What I understand is, in the worst case scenario, the output clock of the PLL would have an incorrect frequency.