Posted on December 12, 2014 at 08:57Hello forum,
I have a weird issue with TIM's pending bits (I mean Cortex-M3 pending bits): they are set after enabling the overflow interrupt:
void InitTIM4() {
TIM_TimeBaseInitTypeDef timer;
TIM_TimeBaseStructInit(&timer);
timer.TIM_CounterMode = TIM_CounterMode_Up;
timer.TIM_Prescaler = 9;
timer.TIM_Period = 79;
TIM_TimeBaseInit(TIM4, &timer);
TIM_Cmd(TIM4, ENABLE);
TIM_ITConfig(TIM4, TIM_IT_Update, ENABLE);
}
Therefore after enabling all interrupts with __enable_irq (), program goes to corresponding Handlers immediately, although it should go there after TIM overflows. I tried clearing pending bits with NVIC_ClearPendingIRQ() but it didn't work. Maybe i'm not understanding or missing something simple, i don't know.
I'm using STM32F100RB MCU.
Sorry for my poor English.
