Board: NUCLEO-H723ZG
MCU: STM32H723ZG (applies to others as well)
Reference manual: RM0468 Rev. 3 Link
Dear community,
I want to do a phase measurement of an approx. 75kHz analogue sine signal with respect to the HSE clock. For that purpose, I aim to trigger the 16-bit ADC1 by a timer TIMx to get regular sampling.
As I need an exact timing to reduce phase noise, I want to use the synchronous mode of the ADC to eliminate trigger jitter.
In section "28.4.3 ADC clocks", the reference manual says:
[...] when adc_sclk is twice faster than the adc_hclk clock, the latency between the trigger and the start of conversion is fixed.
In section "28.7.21 ADC common control register (ADCx_CCR)", Bits 17:16 CKMODE[1:0], the ADC clock mode is described as:
In synchronous clock mode, when adc_ker_ck = 2 x adc_hclk, there is no jitter in the delay
from a timer trigger to the start of a conversion.
Taking into account figure 161 "ADC clock scheme" (see below), the two sentences state different things: adc_sclk (red) can never be equal to adc_ker_ck (yellow), because of the fixed /2 divider in the clock tree. Thus, the two sentences of section 28.4.3 and 28.7.21 are mutual exclusive.
My question is:
How does the ratio of adc_hclk and adc_sclk, respectively adc_ker_ck, have to be chosen to achieve the synchronous mode of ADC1, using a TIMx internal trigger, in a STM32H723 MCU?
Thank you for your help,
Inor
