Posted on December 11, 2014 at 16:26The original post was too long to process during our migration. Please click on the attachment to read the original post.
This is why packets normally have preamble/sync data at the front.
You might want to address the Cortex-M3 hazard in your IRQHandler. Qualify the source of the interrupt, and clear it much earlier, so it isn't the last thing it does before it returns.
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