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Does STM32H7 support ISSI's OctalRAM ?

Lin_Yishan
Associate II

Hello, thank you for reading this post, sincerely hope to help answer questions.

The OSPI interface of STM32H735IGK6 is used to connect ISSI66WVO32M8DBLL to ISSI's PSRAM, which can read and write registers but cannot read and write memory. When configuring the register, it is found that the 24-26-bit MTYP[2:0]:Memory Type in the OCTOSPI device configuration register 1 (OCTOSPI_DCR1) register is controversial. According to the description in the manual, the MTYP[2:0] is shown in Figure 1, while the configurable options in cubemx are shown in Figure 2. Both have bias; Moreover, the following paragraph was found in file AN5050 which did not indicate that the general OSPI interface supports ISSI's PSRAM, please see Figure 3 below, so I would like to confirm whether STM32H7 supports ISSI's PSRAM (the general OSPI interface protocol is not hyperbus).If supported, what mode should this option (memory type) select? Thanks for your answer.

Lin_Yishan_0-1722914304757.png

Figure 1

 

Lin_Yishan_1-1722914481420.png

Figure 2

 

Lin_Yishan_2-1722914559326.png

Figure 3

 

 

 

5 REPLIES 5
KDJEM.1
ST Employee

Hello @Lin_Yishan and welcome to the Community ,

 

The memory type depends on the D0/D1 ordering: The micron (and compatible memories) use D0/D1 Ordering while Macronix (and compatible memories) use D1/D0 data ordering and Macronix RAM (and compatible memories)  use D1/D0 ordering with dedicated address mapping.

If you have a memory different from Micron and Macronix you simply need to look at the data ordering in the memory datasheet and then select the one that matches it in STM32 OSPI configuration.

The ISSI memory is not listed, so you need to look at the data ordering in ISSI memory datasheet and check which mode is compatible.

"ISSI66WVO32M8DBLL": Does you mean IS66WVO32M8?

For ISSI PSRAM IS66WVO32M8 memory is compatible with  OCTOSPI interface when setting Macronix RAM ( MTYP = 011 ).

 Could you please share the memory datasheet?

Thank you.

Kaouthar 

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Thank you for your reply, PSRAM model is indeed ISS66WVO32M8DBLL, I will send the data manual to you below.

 

KDJEM.1
ST Employee

Hello @Lin_Yishan ,

 

Thank you for sharing, I looked at the data ordering in ISSI memory datasheet and I figured it is compatible with Macronix RAM.

KDJEM1_1-1722936860745.png

 

Has your request been answered?

If you need further clarification, please do not hesitate to share it 

If your request is answered, please click on Accept as Solution on the reply which answered your question.

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Thank you for your reply.Modify according to the method you gave, but the problem is still not solved,sincerely hope to help answer questions:

The thing is that I use the OSPI2 interface of the STM32H735 to connect to the ISS66WVO32M8DBLL and use indirect mode for memory reading and writing.
1、The first step is to use cubemx to configure OSPI interface parameters as shown in the following figure:

 

Lin_Yishan_0-1722941868043.png

Lin_Yishan_1-1722941881719.png

Lin_Yishan_2-1722941940890.png

2、The second step is to define the data read and write command parameters with OSPI_RegularCmdTypeDef:

 1.here the write data is 32 bytes and the data is printed out through the serial port

Lin_Yishan_4-1722942075597.png

Lin_Yishan_6-1722942238132.png

2.here read the 32 bytes of data written above 

Lin_Yishan_7-1722942465502.png

Lin_Yishan_8-1722942544488.png

3.The following are the address and instruction parameters for the call, as defined by ISS66WVO32M8DBLL:

Use wrap burst mode

Lin_Yishan_9-1722942747632.png

Lin_Yishan_10-1722942793181.png

Lin_Yishan_11-1722942988933.png

3、I have a few things to add about ISS66WVO32M8DBLL

Lin_Yishan_12-1722943256839.png

1.DQSM operates as a data mask when data is written to memory;

2.DQSM acts as the data synchronization clock when data/registers are read;

Lin_Yishan_13-1722943410823.png

1.Default value: 1111 0000 0010 0010 :0xf022

2.CR[3] Initial Access Latency: When used in conjunction with Latency counter, the multiple of Latency counter is determined. When this bit is 0, the multiple is determined according to whether there is Refresh Collision (Refresh collision means that a read or write operation is performed at the same time during a refresh operation, which may result in performance issues or data errors). Decide that if there is a refresh conflict, it will be twice, and if there is no refresh conflict, it will be 1 times. When this bit is 1, it is fixed to double.

4、The third step, call the above function, the address and data passed in, but the actual print results, read the data is wrong:

Lin_Yishan_14-1722943668605.png

Lin_Yishan_15-1722943759853.png

The above code is to write 32 bytes of data to memory, read it into the array, and print it out through the serial tool.

The results are as follows:

Without changing the memory type (originally AP Memory), the register reads correctly but the memory reads and writes incorrectly,

Lin_Yishan_16-1722944319018.png

Lin_Yishan_17-1722944354770.png

and after changing to Macronix RAM, the register reads and writes incorrectly:

Lin_Yishan_18-1722944590677.png

Lin_Yishan_19-1722944625483.png

I think there may be an error in the register configuration, hope you can answer the doubts, thank you very much!

I will provide my  code.

Hello,

 

You can find the follow-up in Problem with PSRAM peripherals of STM32H735 - STMicroelectronics Community

 

Thank you.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.