Logic SPI config:
CPOL=0 polarity=0
CPHA=0 data is valid on leading edge
Logic diagram: data changes state half a period before first rising edge, sampled at each rising edge and update on each falling edge
so Logic SPI config is correct.
STM32CubeMX config:
CPOL=0
CPHA=1 <- this is incorrect
as the data is sampled exactly when it changes you may sample the old data or the new data. This explains shift in data and inconsistent results.
Configure CPHA=0 and it should work.
Edit:
I was wrong. In STM32CubeMX "CPHA=1 edge" means CPHA=0.
CPU clock and peripheral clock seem sufficient at 64MHz/32MHz for a 1MHz SPI signal.
Have you checked the voltage of the signal? Perhaps voltage level or rise time of the signal is not sufficient. The Logic analyzer might see the right signal, but the MCU might not or vice versa.
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