2015-10-22 02:47 AM
Hello,
I would like to program an external flash (S29GL128S10) connected to the STM32F429 at address 0x64000000 using the ST-LINK Utility.
I didn't find an external Loader for this need so I am trying to create it using the examples and the module STM32F4xx_hal_nor.c from Cube V1.8.0But I am a little lost with the ''NOR memory internal address'' parameter in some functions of the module STM32F4xx_hal_nor.c
In the function HAL_NOR_ReadBuffer()
* @param uwAddress: NOR memory internal address to read from. But in the line: *pData++ = *(__IO uint16_t *)uwAddress; uwAddress should be the full addressIn the function HAL_NOR_ProgramBuffer()
* @param uwAddress: NOR memory internal start write address NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1)); uwAddress must be the internal address: ok but some lines later p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); NOR_WRITE(p_currentaddress, *pData++); p_currentaddress should be the full addressIt seems to me that these functions should not work.
In the function HAL_NOR_Erase_Block() What should be the difference between the Address parameter and the deviceaddress data.Thanks
2015-10-22 06:10 AM
For a 16-bit NOR the address bus is shifted on the STM32, the A0 pin of the NOR is actually the A1 from the processors perspective. The NOR device has a number of magic addresses/constants that must be sequenced to the chip. So 0x2AAA must be shifted left once so that exact pattern is presented to the chip at it's interface pins.
2015-10-22 06:56 AM
Thanks Clive,
My trouble is the definition of the parameter uwAddress (NOR memory internal address to read from) in the STM32F4xx_hal_nor.c module and its use
*pData++ = *(__IO uint16_t *)uwAddress; I think it should be *pData++ = *(__IO uint16_t *)(deviceaddress + uwAddress); Or using the MACRO *pData++ = *(__IO uint16_t *)NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B/16B, uwAddress);Regards,
For a 16-bit NOR the address bus is shifted on the STM32, the A0 pin of the NOR is actually the A1 from the processors perspective. The NOR device has a number of magic addresses/constants that must be sequenced to the chip. So 0x2AAA must be shifted left once so that exact pattern is presented to the chip at it's interface pins.
2015-10-22 10:13 AM
I'm not looking to get into the HAL implementation. The NOR memory is within the regular addressing space of the processor and can be directly accessed as such.
The Write/Erase require some gyrations when communicating with the NOR part that need specific offsets.