Nested interrupts on the Nucleo-F411RE

[carlosdelfino]

I am doing an academic activity where I was asked to execute a reading process from an external RTC via i2C, but on another MCU, I used a repeat timer, but I was unsuccessful. Something seems to interfere with the I2C communication and according to the analyzer (I am using a didactic simulator) the bus clock signal is not generated, but I see a series in the data signal exactly at the programmed time, so the firmware seems to freeze when writing to the I2C bus.

On an STM32 (especially on the Nucleo Nucleo-F411RE board) is it possible to nest the communication inside a repeat timer interrupt? I did not get to know in my studies on STM32 about which timers exist, which document should I read to learn more about this subject?

[Tesla DeLorean]

On the NVIC you can describe the "grouping" of bits describing a priority level and a preemption level, things with a lower preemption number can interrupt those other interrupt, otherwise they stack,and as you exit one IRQ Handler, it "tail-chains" into the next.

Joseph Yiu's "Essential Cortex-M3" and related book series covers this material.

With SysTick you ideally want it to preempt in HAL so the tick-count for timeouts works well. HAL call-backs occur in interrupt context, so you don't want to call blocking functions.

BTW you can put hyperlinks in signatures via <a href="url">describe</a>

[carlosdelfino]

I haven't yet gotten to the point in my studies on how to prioritize interrupts.

I have a lot of respect for Joseph Yiu, I have the book Definitive Guide To ARM Cortex-M23 and Cortex-M33 Processors.

I don't know if the NVIC of the Cortex-M33 is the same as that of the Cortex-M4 (stm32-f411re), but I'm going to dedicate a special reading to this section.

But if you have an example that you can give me to shorten this path, it would be of great help.