Multiple bus master access to OSPI PSRAM on STM32L4P5G-DK

[JSchu.5]

I'm using a STM32L4P5G Discovery Kit board with the external OctoSPI PSRAM in memory mapped mode to store a framebuffer for a SPI display. The board runs at 120MHz and uses the board support file by ST for initialization. The SPI transfer to the display is managed by DMA1. The given setup is working as expected. Now if I place other data in the external PSRAM and access the data during DMA Transfer the display update stops. The same effect occurs if I use my debugger to show frame buffer memory during transfer. I checked the bus matrix of L4 in the AN4760. I expected the OSPI peripheral to synchronize memory read and write requests by different bus masters. Am I wrong?

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I discovered the effect because the grpahic library crashes from time to time at different points. If I place the data of the graphic library in the controller SRAM everything is working as expected.