Mixed interrupts in the vector table
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‎2024-04-05 12:26 AM
Hello,
I'm looking the vector table described in the Table 97 of the STM32G4 series reference manual, and it shows interrupts with different characteristics, such as TIM1_BRK/TIM15 and TIM6_DACUNDER, being allocated to the same address.
This is very confusing to me because I first thought TIM1 and TIM15 have something to do with a master/slave relation, but it was not.
My question is why are these confusing definitions happen. Is that due to the hardware constraints of the Cortex core?
Thanks,
macalon
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‎2024-04-05 2:33 AM - edited ‎2024-04-05 2:52 AM
Hello,
This is not the only example where an interrupt vector supports more then one interrupt request. Many STM32 MCU products have this implementation.
It was a design choice as the peripherals are increasing with many interrupt request outputs. The interrupt source is managed by software.
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‎2024-04-05 2:33 AM - edited ‎2024-04-05 2:52 AM
Hello,
This is not the only example where an interrupt vector supports more then one interrupt request. Many STM32 MCU products have this implementation.
It was a design choice as the peripherals are increasing with many interrupt request outputs. The interrupt source is managed by software.
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‎2024-04-05 5:42 PM
Thank you!
