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Arjun Oberai
Associate II
January 18, 2018
Question

Maximum Timeout for Window Watchdog(WWDG)

  • January 18, 2018
  • 1 reply
  • 1457 views
Posted on January 18, 2018 at 06:44

I have a question regarding the WWDG in STM32F103RB.

  • What can be the maximum timeout using the WWDG or even better question will be what will be the optimum value of the APB1 clock period(ms).

I know the Maximum value of the APB1 clock can be 36 MHz. I suppose using the least value of the APB1 will give us the max timeout, but I am not able to figure what can it be. 

#watchdog #wwdg #stm32
This topic has been closed for replies.

1 reply

Danish1
Lead III
January 18, 2018
Posted on January 18, 2018 at 10:05

From the reference manual, section on Reset and Clock-control

APB1 frequency is determined by a pre-scaler/divider from AHB frequency; the divider can be 1, 2, 4, 8 or 16.

AHB frequency is determined by a pre-scaler/divider from SYSCLK; the divider can be 1, 2, 4, 8, 16, 64, 128, 256 or 512.

So how slow APB1 can be depends how slow you can run your processor and AHB bus.

Personally, I wouldn't normally run the processor slower than 8 MHz because that's what it starts at.

And from 8 MHz / 512 / 16 = 976 Hz approx.

Hope this helps,

Danish

Arjun Oberai
Associate II
January 18, 2018
Posted on January 18, 2018 at 12:00

Thank You Danish, that was a comprehensive reply that clears my doubt.

Cheers,

Arjun Oberai