Maximum SRAM usage on STM3220G-EVAL

[rgrimes]

Posted on August 10, 2011 at 22:55

How much is there, really?  And how much is really available?

The specs all say 16 mbit, but the part and the schematic show 32 mbit, or 4 MBytes.  Looking into the code examples include with IAR EWARM, it seems only A0-A17 are assigned to the FSMC, which suggests only 256 KBytes?! However, in the debugger there appears to be 512 KBytes of actually usable memory!  So, here are my questions:   1. How much memory is actually usable?   2. How do I set up access to all of it? Thanks!

[Tesla DeLorean]

Posted on August 11, 2011 at 02:31

For the STM3220F-EVAL

http://www1.futureelectronics.com/doc/STMICROELECTRONICS/STM3220G-EVAL.pdf The straight SRAM has 18 address bits, and is 16-bits wide. ie 256Kwords or 512Kbytes or 4Mbits A0..17 are shifted versions of A1..18 It's access time is 55ns, so figure about 7 times slower than internal SRAM. For the STM3220G-EVAL http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/USER_MANUAL/DM00022972.pdf The straight SRAM has 21 address bits, and is 16-bits wide. ie 2048Kwords or 4096Kbytes or 32Mbits (CY7C1071DV33) A0..20 are shifted versions of A1..21 It's access time is 12ns, so figure about 2 times slower than internal SRAM. It might be fitted with a smaller, slower, or faster part. The IS61WV102416BLL-10MLI is a 1024Kword, 2048Kbyte, 16Mbit part. At 10ns it's still at least 2 cycles. http://www.issi.com/pdf/61WV102416ALL.pdf I suspect you'd program the pins to associate with the FSMC, and you'd program the FSMC with the geometry of the device.

[rgrimes]

Posted on August 11, 2011 at 13:24

Aha!

The key point you made is contained in the phrase ''A0..17 are shifted versions of A1..18'' (and the related point for my board), which explains the 256K/512K discrepency I noticed.  I am also willing to readily believe that the code samples are intentionally compatible with the older board with the smaller SRAM. In my confusion and rush to get out a question before leaving for the day, it didn't occur to me that they would have done that ''shifting''; it seems more natural to me to label the signals A1..18.  But that's just me... Now, I've got to figure out how to get those extra address bits mapped... Thanks, Clive1!!! -Bob

[Tesla DeLorean]

Posted on August 11, 2011 at 16:31

Yes, on things like the 68K we had to play games with the address pin names on the schematic depending on the parts and the bus widths. I suspect the STM32 with it's pin constraints, and to simplify the schematics, went with a more dynamic scheme. Just another thing to watch out for.

A quick dig around didn't find a good FSMC example, mostly ''too be implemented i next version'' Confirming to myself it was really a 55ns part, not a 5.5ns one http://www.issi.com/china/pdf/66WV25616ALL-BLL.pdf