Maximum ADC clock frequency?

[dusan2]

Posted on March 28, 2013 at 12:18

Hi!

I have a question regarding the maximum clock frequency for the ADC. The data sheet on STM32F407 gives maximum clock frequency for ADC as 36 MHz (Doc ID 022152, Rev 3, page 124) for power supply of 3.6 V. However, there are examples at ST site that use higher clock frequency of 168/4 = 42 MHz. This is the case in the latest version of Standard Peripheral Library package (''stm32f4_dsp_stdperiph_lib.zip'' obtained today from the ST site), but not the case in the ''STM32F4-Discovery_FW_V1.1.0'' package (where correct ''system_stm32f4xx.c'' file defining the ADC clock at 36 MHz is used). Which of the two clock frequencies should I use: 36MHz or 42 MHz? I have tested the ADC using both clock frequencies and the shortest sampling time of 3 clock periods, but noticed no difference regarding the resolution or missing codes of the ADC. The point here is that the requirement to use the 36 MHz clock for ADC reduces the clock frequency for the CPU from 168 to 144 MHz, and therefore slows down the execution of the program for about 15%. My application includes sampling at about 1 MHz and on-line filtering. Speed here is of importance. Thanks and best regards #adc-clock-frequency

[Tesla DeLorean]

Posted on March 28, 2013 at 13:36

Ok, but you could still run the CPU at 168 MHz, if you dropped the ADC speed to 21 MHz via it's prescaler.

[dusan2]

Posted on March 28, 2013 at 14:37

Thanks for the suggestion. In that case I can still use sampling of 3 clock periods, and 12 bit conversion takes additional 12 clock periods. This means that the conversion is finished in 0.71us ==> 1.4 Ms/s; fast enough.

I have another question. The complete conversion takes 15 clock periods minimum. In case I use two ADCs to sample the same input signal and run ADCs in interleaved mode, continuously, I need to specify the delay between the sampling times of both ADCs. Since the conversion time is an odd number of clock periods, how should I define the delay to make time intervals between successive (but taken with alternate ADCs) samples equal? Thanks for your time.

[Tesla DeLorean]

Posted on March 28, 2013 at 17:08

Then you'll likely have to compromise, or use triple interleave mode. The power of 2 dividers used by ST are rather limiting in this regard. Running at 160 MHz might prove sufficiently accommodating.

The original DSP examples used 144 MHz, but as you say the newer ones are at 168 MHz. The new library also has support for the 2MB parts which can run at 180 MHz. Someone from ST will have to answer whether 42 MHz for the ADC is viable, a question perhaps best directed at an ST rep or FAE

[dusan2]

Posted on April 02, 2013 at 08:05

Thanks, I will do this (ask ST).

Regarding the 21 MHz clock again: Suppose one of the timers triggers the start of conversion for an ADC. The timer runs from an 84 MHz clock, and starts a conversion (SC). When will the ADC respond to the SC and start sampling? Instantly? On first ADC clock (21 MHz) transition? Will the difference in clock frequencies additionally disperse the time interval between two consecutive conversions? The solution might be to run the timer at 21 MHz as well...