M2M DMA transfer to FMAC->WDATA fails, but individual writes to WDATA work. Is M2M supported for loading X1?

[KHarb.1]

I've finally got the FMAC to load, execute and produce data. However, I can only make the X1full flag get set if I call 16 writes to WDATA. I'd like to streamline part of this and use a memory to memory transfer. I'm seeing this not working. Can memory to memory transfers be used to load the X1 buffer with multiple values?

I'm using this line to test:

HAL_DMA_Start(&hdma_memtomem_dma1_channel5,(uint32_t)CTST_IN,(uint32_t)&FMAC->WDATA,16);

Source address is configured to increment and the destination address is not. This should generate repeat writes to WDATA from the elements in CTST_IN. I can't tell what if anything is written to the FMAC.

If I change &FMAC->WDATA to a generic R\W register (I used TIM20->CCR6) I can read back the last data item in the buffer from CCR6, [correct] so I know the DMA channel and transfer work.

I suspect I'll run into other circumstances where repeat register writes are used to load a buffer. Is it a common condition that memory to memory transfers can be used this way?

[BarryWhit]

You're confusing "memory-mapped" with "memory".  

[KHarb.1]

I don't follow.  FMAC->WDATA is a mapped register I want to write to repeatedly from values held in an array that is stored in SRAM. Where's the confusion?