JTAG unable to attach to CPU

[optifier]

Posted on March 08, 2013 at 22:24

Hello ST community, first forum post...

We're having problems with downloading EVAL example code into STM32F207ZC. I've soldered 144-pin chip to an adapterboard and followed schematics in AN3320 ''Getting started with Hardware development'' document. All Vdd and Vss are connected, also VddA and VssA. All recommended caps in place. 25MHz crystal mounted. We use J-Link v8.0 from IAR. We have two, both give same error messages. Both work flawless for Atmel SAM7 which we want to replace with ST MCU. In order to open EVAL project in IAR Workbench we had to download the latest version 6.5. We have compiled an example from Standard Peripheral Library which should output PWM signal using TIM10. Changed Device to MCU we're using inside IAR Workbench. Of course we've tested all pin connections on adapterboard numerous times and all seem correct. No pins except JTAG and RST pins are connected to anything. We also scoped JTAG pins and they all wiggle when trying to download except nJTRST which as far as I understand is expected. RST pin is pulled low several times by JTAG during attempt to contact MCU. Workbench Messages: ''Failed to get CPU status after 4 retries'' ''Failed to load flash loader C:\...\Embedded Workbench 6.5\arm\config\flashloader\ST\FlashSTM32F205xC.flash'' ''Bad JTAG communication: Write to IR: Expected 0x1, got 0x2 (TAP Command : 10 @ Off 0x5)'' Workbench Log: Fri Mar 08, 2013 10:28:37: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\ST\FlashSTM32F2xxxx.mac Fri Mar 08, 2013 10:28:37: JLINK command: ProjectFile = C:\data\p-1026-lockkort\stm32f2xx_stdperiph_lib\STM32F2xx_StdPeriph_Lib_V1.1.0\Project\STM32F2xx_StdPeriph_Template\EWARM\settings\Project_STM322xG_EVAL.jlink, return = 0 Fri Mar 08, 2013 10:28:37: Device ''STM32F207ZC'' selected (256 KB flash, 64 KB RAM). Fri Mar 08, 2013 10:28:37: DLL version: V4.64a, compiled Feb 25 2013 18:26:59 Fri Mar 08, 2013 10:28:37: Firmware: J-Link ARM V8 compiled Nov 14 2012 22:34:52 Fri Mar 08, 2013 10:28:37: JTAG speed is initially set to: 32 kHz Fri Mar 08, 2013 10:28:37: TotalIRLen = 9, IRPrint = 0x0011 Fri Mar 08, 2013 10:28:37: STM32F2xxx/STM32F4xxx: Can not attach to CPU. Trying connect under reset. Fri Mar 08, 2013 10:28:37: TotalIRLen = 9, IRPrint = 0x0011 Fri Mar 08, 2013 10:28:37: Hardware reset with strategy 0 was performed Fri Mar 08, 2013 10:28:37: Initial reset was performed Fri Mar 08, 2013 10:28:37: TotalIRLen = 9, IRPrint = 0x0011 Fri Mar 08, 2013 10:28:37: STM32F2xxx/STM32F4xxx: Can not attach to CPU. Trying connect under reset. Fri Mar 08, 2013 10:28:38: TotalIRLen = 9, IRPrint = 0x0011 Fri Mar 08, 2013 10:28:38: TotalIRLen = 9, IRPrint = 0x0011 This is done numerous times Fri Mar 08, 2013 10:28:38: STM32F2xxx/STM32F4xxx: Can not attach to CPU. Trying connect under reset. Fri Mar 08, 2013 10:28:38: TotalIRLen = 9, IRPrint = 0x0011 Fri Mar 08, 2013 10:28:38: TotalIRLen = 9, IRPrint = 0x0011 and when we end debug session Fri Mar 08, 2013 10:28:54: Fatal error:    Session aborted! Fri Mar 08, 2013 10:28:54: Failed to load flash loader: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\ST\FlashSTM32F205xC.flash This is our first time testing ST processor, we've used example code for EVAL board. Copied PWM code example to Template folder as explained in readme.txt. We've not done any changes to any files. Proper device is chosen inside Workbench and JTAG seem to adapt to this. Are there any other required changes to run EVAL code from our own PCB? Were having some doubts around how to configure BOOT0..1 pins. We don't have any bootloader to install yet and I guess?? that the factory programmed bootloader is unused when download is done via JTAG. Do we need to configure these pins to a correct state in order to make JTAG download work? (we've tried all 3 options but ''normally'' stick with Flash option) Any other suggestions why this would fail? Regards, Richard #jtag-iar-bootloader

[Tesla DeLorean]

Posted on March 09, 2013 at 00:57

How about the VCAPx pins, do you have capacitors on them? What voltage do you see. I think the last person with chronic problems had Pin 1 misidentified. Check also than NRST of  a powered board, no JTAG, is high.

Humor us with a circuit diagram, redacted as needed. Problems with JTAG usually revolve around power, or connectivity. Try also SWD mode. You could also use the JLINK console, this should give an indication of connectivity, without involving IAR. You could pull BOOT0 high, but a blank device should still access ok. You might want to use this trick if the core goes to low power, or your code reconfigures or disables JTAG pins, etc.

[optifier]

Posted on March 09, 2013 at 02:43 ________________ Attachments : reference_schematic.jpeg : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtVA&d=%2Fa%2F0X0000000aQv%2FESjdldbxViwzjKUjQpxkjkDwW2e0Hjbkxj_OKMrhDRc&asPdf=false

[Tesla DeLorean]

Posted on March 09, 2013 at 05:45

So in principle it should work, but it doesn't. If you want me to look it over I need a circuit diagram, and pinning, that you've actually implemented.

The 1V2 regulator seems to be functioning, which is a good sign. I guess you should probably concentrate on the JTAG interface, and pining of the connector. A J-Link pushes 5V out of pin 19. One other tack would be to connect USART1 (PA9,PA10), and BOOT0 high, reset and then ping the chip with an 0x7F byte at 9600 8E1, and see if you can illicit an 0x79 response. If that fails, then we need to assume the chip is not running, and go back to the supplies/reset.

[optifier]

Posted on March 09, 2013 at 16:20

[jj2]

Posted on March 09, 2013 at 17:17

Sadly - such prototyping efforts - especially on so complex/multi-pinned device - frustrate, delay, and too often ''fail'' to deliver ''hoped for'' cost savings.

Suggest 2 alternatives with better odds: a) standard Eval board targeting closest MCU to your desired b) design & production of 3-5 ''MCU + support components'' (just the essence) pcb and ''fill'' of the MCU by qualified, smt proto assembly house.  (we always build in multiple to guard against ''single board anomaly'')  These advanced package types are not ''proto-friendly'' - this (failed) story has too often been repeated - believe proposal here is ''better way.''

[Tesla DeLorean]

Posted on March 09, 2013 at 19:15

a) standard Eval board targeting closest MCU to your desired

And for breakout exercises there are a number on eBay that work with F2/F4 without the clutter of the peripherals attached to the STM32F4-Discovery, which will take 207,217,417, and presumably some of the 42x/43x series 2MB parts.

http://www.ebay.com/itm/Core207V-STM32F207VCT6-STM32-ARM-Cortex-M3-Development-Board-Full-I-O-Expander-/261045964487?pt=LH_DefaultDomain_0&hash=item3cc78d4ec7

http://www.ebay.com/itm/STM32F207ZG-module-HY-STM32F2xxCore144-Core-Dev-Board-/170874320152?pt=LH_DefaultDomain_0&hash=item27c8e73518

[optifier]

Posted on March 09, 2013 at 19:42