Posted on September 19, 2017 at 23:30
Hello!
For the first issue, DR,TR,SSR registers have shadow registers. The read from shadow registers controlled by BYPSHAD bit in CR register. This bit must be zero when you read the calendar, time and/or subseconds as unity.
The shadow registers updated every 2 RTC clock periods .(so your resolution will not be 1/32768)
To read the shadow registers must wait for RSF bit in RTC_ISR register to set.(must be cleared before wait) This indicates that shadow registers are ready for read.
HAL_RTC_WaitForSynchro(..) function waits for this RSF bit.
Note that RSF bit must be cleared by software.
So.. some pseudocode for reading RTC
Init RTC..(also clears the RSF)
BYPSHAD=0;
while(1)
{
wait for RSF;
Read SSR first (locks the higher order shadow registers)
Read Time
Read Date
Clear RSF
Use the calendar
}
For the second issue, RTC_OUT is not 1 HZ because the 1HZ freq taken from fRTCCLK/(256 * (PREDIV_A+1)) =128
The PREDIV_A=0.
Regards
vf
Posted on September 20, 2017 at 12:00
Thanks for your reply.
Results observed from RTC_OUT is then consistent, reference manual is confusing because RTC block diagram:
shows ck_spre is connected to RTC_CALIB and
Concerning shadow register read I enhanced my code with HAL_RTC_WaitForSynchro(). In my HAL RTC driver version (1.7.2) this function clears RSF bit and wait it to be set. Then my code is:
HAL_RTC_Init(...)
HAL_RTC_SetTime(...)
HAL_RTC_SetDate(...)
HAL_RTCEx_DisableBypassShadow(...)
onAlarmA()
HAL_RTC_AlarmAEventCallback()
{
onAlarmA()
}
onAlarmA:
HAL_RTC_WaitForSynchro(...)
HAL_RTC_GetTime(...)
HAL_RTC_GetDate(...)
Compute next alarm
HAL_RTC_SetAlarm_IT(...)
Next alarm is approximately 250ms later. I still see alarm A is sometimes not triggered. I saved Time and Date from RTC in Timestamp table and I see timestamp inconsistency as explained before.
What am I doing wrong?
Posted on September 20, 2017 at 12:38
Always get a current version of the RM you are working with:
It correctly depicts the RTC_CALIB to be outputs from the dividers - the ''512Hz'' is obviously a tap from the 6th bit of async divider and the ''1Hz'' is a tap from the 7th bit of the sync divider (ST: the narrative might say so, not just having described behaviour when mägic values are present in the prescaler regiters).
Timestamp retrieved from RTC are sometimes inconsistent: seconds register did not increment while subseconds register reached 0 and rolled over.
Errata to other families contain a RTC calendar registers are not locked properly erratum, I'd bet it applies to 'L4xx too, even if it is not in the current STM32L4x6xx Errata sheet, April 2017 DocID026121 Rev 5...
Quiting from the 'F40x errata:
Description
When reading the calendar registers with BYPSHAD=0, the RTC_TR and RTC_DRregisters may not be locked after reading the RTC_SSR register. This happens if the readoperation is initiated one APB clock period before the shadow registers are updated. Thiscan result in a non-consistency of the three registers. Similarly, RTC_DR register can beupdated after reading the RTC_TR register instead of being locked.Workaround1. Use BYPSHAD = 1 mode (Bypass shadow registers), or2. If BYPSHAD = 0, read SSR again after reading SSR/TR/DR to confirm that SSR is stillthe same, otherwise read the values again.JW
