Is there an output-on-tamper pulse when the RTC alarm is triggered in Vbat mode?

[HAbay.1]

I want to use an SR latch to detect the alarm pulse on the tamper pin ( STM32F103C8T6), is this possible in Vbat mode? if it is, then what amplitude is this pulse (I am asking because it might be possible that the pulse wasn't high enough for the sr latch to detect it).

[waclawek.jan]

The behaviour of this pin is controller by BKP_RTCCR.ASOE and BKP_RTCCR.ASOS bits, while tamper must not be enabled in BKP_CR.TPE. Read out these registers and check.

Output current of PC13 is limited, see datasheet.

JW

[HAbay.1]

yes I am aware of that , what I am uncertain of is whether the tamper pin keeps working as intended in VBat mode which doesn't seem to be the case.

[waclawek.jan]

So you see it working while both VBAT and VDD is connected, and then it stops working when VDD is removed and only VBAT remains?

JW

[HAbay.1]

yes .

[waclawek.jan]

Can you please read out and post RTC, BKP and RCC_BDCR registers content.

JW

[HAbay.1]

if you were referring to the registers I used in my code then there they are, ( RTC LSE setup function)

void RTC_SETUP_LSE(uint16_t CNTL,uint16_t CNTH,uint16_t ALRL,uint16_t ALRH){
	//ENABLE RTC PWR CONTROL
			RCC->APB1ENR |= (RCC_APB1ENR_PWREN);
			//ENABLE backup registers
				RCC->APB1ENR |= (RCC_APB1ENR_BKPEN);
				//Enable write to backup domain
				PWR->CR |=PWR_CR_DBP;
				//ENABLE RTC
				RCC->BDCR|=RCC_BDCR_RTCEN;
				//LSI OFF
					RCC->CSR &= ~(RCC_CSR_LSION);
					//LSE ON
					RCC->BDCR |=RCC_BDCR_LSEON;
				while(!(RCC->BDCR & RCC_BDCR_LSERDY));
					//choosing LSE for THE RTC
					RCC->BDCR |=RCC_BDCR_RTCSEL_LSE;
					//ASOE ASOS OUT TAMPER
					BKP->RTCCR |=BKP_RTCCR_ASOE;
					//OUTPUT FREQUENCY
					//need to clear ASOS AND ASOE
					//BKP->RTCCR &=(~(BKP_RTCCR_ASOS));
					//BKP->RTCCR &=(~(BKP_RTCCR_ASOE));
					//BKP->RTCCR |=BKP_RTCCR_CCO;
		//waiting for ABP1 TO BE SET BY HARDWARE
		RTC->CRL &=(~(RTC_CRL_RSF));
			while(!(RTC->CRL & RTC_CRL_RSF));
		//waiting for the last operation to finish
		while(!(RTC->CRL & RTC_CRL_RTOFF));
		//ENABLE CONFIG
			RTC->CRL|=RTC_CRL_CNF;
		//1 Second interrupt enable
			RTC->CRH |=RTC_CRH_SECIE;
		//PRESCALER VALUE
			RTC->PRLH &=~(15);
			RTC->PRLL=32768-1;
		//Alarm IR enabled
			RTC->CRH|=RTC_CRH_ALRIE;
		//alarm ir value
			RTC->ALRH=ALRH;
			RTC->ALRL=ALRL;
		//DATE
			RTC->CNTL=CNTL;
			RTC->CNTH=CNTH;
		//disable config
			RTC->CRL&=(~(RTC_CRL_CNF));
			//waiting for the last operation to finish
			while(!(RTC->CRL & RTC_CRL_RTOFF));
			//disable write to backup domain
					PWR->CR &=(~(PWR_CR_DBP));
 
 
}

[waclawek.jan]

Thanks, but can you please read out the content of those registers, and post.

JW

[HAbay.1]

I'm sorry I don't really understand your request , do you mean the actual bits these registers have from the reference manual? or something else perhaps?

edit: if you're asking about the state of these registers when the code is running then they all have their respective, assigned values from the code in standby mode and run mode(code functions flawlessly), i do not know if that's the case for vbat the rtc counter is definitely still running( and i don't really know how to make sure the bits are assigned properly in vbat mode any tips on that will be greatly appreciated).

[waclawek.jan · Accepted solution]

> edit: if you're asking about the state of these registers when the code is running

Yes, I'm asking you to read out those registers and post their content here.

Sometimes registers don't contain what you've written into them, for example if you don't obey some (not always published) timing rules. Also, you surely have code which you don't show us, which may influence these registers. The mcu works out of the registers' content, so checking the actual content of registers is the first thing to do before looking into more obscure reasons for some feature not working.

Also, did you verify LSE and RTC are running while in VBAT mode and is the clock to , i.e. were there (missed) alarms during VDD was off?

JW