Is the word(uint32_t) access atomic in shared memory in dual core STM32H7

[yhplx]

Hi Friends,

In STM32H7 MCU, both M7 and M4 can access shared memory, such as D3 SRAM4. I am going to use a D3 SRAM4 address as a place to share some status information between M7 and M4. If a 32bits word is defined shown as below,  can the access from both sides(M7 and M4) be guaranteed atomic?  Does it need HSEM?

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Code example:

volatile uint32_t *status_ptr = (status4_7 *)0x38000000;

In M4 side,  *status_ptr = 0x1234abcd;

In M7 side, uint32_t status = *status4to7_ptr;

I know a 32bits word access is atomic in single core STM32 MCU. 

Thank you in advance.

[TDK]

I don't think this is nearly as complicated as it's being made out to be. There are many programming constructs that can work out here, safely. And a lot of the things being mentioned here are true whether your use HSEM or an atomic word access for synchronization.

Volatile keyword definitely has an impact here, and is required in cases where you're constantly polling for a value that is changed by the other core or thread.

[Pavel A.]

> Even with Strongly-Ordered you cannot grantee that as the access of the two cores is asynchronous

So is there a definite recommendation from ST? Use MPU to tweak the shared area?

Cortex-M has notion of "shared" memory, especially "shared device". But IIRC how it works on a specific device depends on its implementer (ST)?

Write and read-back to non-cached area should ensure that a write sinks thru. Is this all we have?

[SofLit]

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Volatile keyword definitely has an impact here, and is required in cases where you're constantly polling for a value that is changed by the other core or thread.

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This is true when one CPU. Here we have two CPUs accessing the same zone. Polling for a value let's say a status set by M4 and read by M7 (polling on it) or vise versa, "volatile" doesn't prevent for safety issues as it's seen only on one core but not (propagated) on the other.